High-Voltage IO Circuit Bias Stabilization Using Compensation Capacitors
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Solution Overview
Problem
High voltage input/output (IO) circuits in integrated circuits face challenges in stabilizing bias voltages due to parasitic capacitances, leading to jitter in output signals and increased size of the IO circuit, when implemented with low voltage transistors.
Innovation Solution
The use of a pre-reverse switch and a post-reverse switch, each comprising capacitors that counteract the coupling effects of parasitic capacitances on bias voltages, maintaining bias voltage stability and reducing jitter in the main-driver output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low voltage transistors are used in high voltage IO circuits, then throughput performance and density are improved, but bias voltage stability deteriorates due to parasitic capacitance coupling
Solution Approach 1:
The patent introduces compensation capacitors as intermediary elements that mediate between the parasitic capacitance effects and the bias voltages. These compensation capacitors are strategically placed to counterbalance the coupling effects, allowing the low voltage transistors to maintain both high performance and bias voltage stability simultaneously.
Solution Approach 2:
The patent applies preliminary anti-action by pre-configuring compensation capacitors that anticipate and counteract the parasitic capacitance coupling effects before they can destabilize the bias voltages. This proactive compensation mechanism ensures that the bias voltages remain stable despite the presence of low voltage transistors with inherent parasitic capacitances.
2Ease of manufacture
If low voltage transistors are used in high voltage IO circuits, then fabrication cost and device density are improved, but output signal quality deteriorates due to jitter
Solution Approach 1:
The compensation capacitors serve as intermediary elements that filter and stabilize the output signals from low voltage transistors. By placing these capacitors at strategic points in the circuit, the patent eliminates jitter and signal quality issues while maintaining the cost and density advantages of low voltage transistor fabrication.
Solution Approach 2:
The patent converts the harmful parasitic capacitance effects into a beneficial compensation mechanism. By intentionally adding compensation capacitors with values designed to counterbalance the parasitic effects, the patent transforms what would be a source of jitter and signal degradation into a mechanism that enhances output signal quality while retaining the manufacturing advantages of low voltage transistors.
3Stability of the object's composition
If bias voltages are stabilized using large capacitors or static current, then bias voltage stability is improved, but IO circuit size increases
Solution Approach 1:
The patent changes the parameter approach from using large capacitance values or high static currents to using precisely calculated smaller compensation capacitor values. By optimizing the capacitance parameters of the compensation capacitors to specifically counterbalance the parasitic effects, the patent achieves bias voltage stability with minimal area overhead, avoiding the need for large stabilizing components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of parasitic capacitances on bias voltages, maintaining stability and minimizing the size of the IO circuit while improving signal quality and switching rates.
Implementation Method 1
The use of low voltage transistors in high voltage IO circuit causes coupling of transitions in high voltage output signal to the bias voltages through parasitic capacitances of the low voltage transistors
Implementation Method 2
The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage
Data Source
AI summary
A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO circuit includes a pre-reverse switch, a main-driver and a post-reverse switch. The pre-reverse switch includes a first capacitor and a second capacitor. The main-driver includes a first parasitic capacitance and a second parasitic capacitance. The post-reverse switch includes a third capacitor and a fourth capacitor. The first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic capacitance on the second bias voltage.