HV JFET Embedded Layer Stabilizes Pinch-Off Voltage

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Solution Overview

Problem

High-voltage junction-gate field-effect transistors (HV JFETs) face variations in pinch-off voltage due to low doping levels in high-voltage N-type wells, affecting their performance in high-voltage applications like switch mode power supplies, where efficiency and low standby power consumption are crucial.

Innovation Solution

The semiconductor device incorporates a substrate with heavily-doped regions and an embedded layer of opposing conductivity type, which helps in creating a depletion region that confines current flow near the surface, reducing the impact of substrate depth and improving pinch-off voltage stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If an HV NWell with low doping level is used to serve as a channel in an HV JFET, then high voltage operation is achieved, but variations in pinch-off voltage significantly increase

Engineering Contradiction:
Improvehigh voltage operation capabilityVSAvoidpinch-off voltage stability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent applies local quality by creating an embedded layer with higher doping concentration specifically in the region beneath the source heavily-doped region, while maintaining lower doping levels in other channel regions. This localized doping enhancement stabilizes the pinch-off voltage without compromising the overall high voltage operation capability of the HV JFET.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping concentration parameter locally by forming an embedded layer with higher doping concentration (1E16 to 1E18 atoms/cm³) beneath the source region, compared to the surrounding channel region doping concentration (1E15 to 1E17 atoms/cm³). This parameter change stabilizes the electric field distribution and reduces pinch-off voltage variations while maintaining high voltage operation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If an embedded layer with higher doping concentration is formed beneath the source heavily-doped region, then pinch-off voltage stability is improved, but device structure complexity increases

Engineering Contradiction:
Improvepinch-off voltage stabilityVSAvoidembedded layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the embedded layer with higher doping concentration during the initial fabrication process, specifically by implanting dopant atoms through the substrate before forming the NWell structure. This preliminary doping action simplifies subsequent processing steps while achieving the desired pinch-off voltage stability.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the stability and efficiency of HV JFETs by maintaining high voltage operation while reducing variations in pinch-off voltage, thus improving the overall performance and reliability in high-voltage applications.

Implementation Method 1

an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region

Methodology Applied
Scientific EffectDepletion region formation: Electric Field

Implementation Method 2

a third heavily-doped region formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, the third heavily-doped region having the second conductivity type

Methodology Applied
Scientific EffectJunction formation: Electric Field

Data Source

PatentUS9299857B2Semiconductor device
Publication Date: 2016.03.29 MACRONIX INTERNATIONAL CO LTD
  • US9299857B2 patent drawing
  • US9299857B2 patent drawing
  • US9299857B2 patent drawing

AI summary

A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type.