High-Voltage Low-Voltage CMOS Integration Structure
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Solution Overview
Problem
The integration of low-voltage and high-voltage MOS devices in semiconductor structures is challenging due to incompatibility, leading to separate integrated circuits, which are costly and inefficient in terms of fabrication and integration density, necessitating a novel structure that reduces the number of photomasks and lithography processes.
Innovation Solution
A semiconductor structure comprising a high-voltage MOS device region with a light-doping region and a well in the substrate, where the conductive type of the light-doping region is similar to the substrate, and a gate stack is formed over parts of these regions, with heavy-doping regions implanted on either side, allowing for a common substrate implementation using fewer photomasks and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate integrated circuits are used for low-voltage and high-voltage devices, then device functionality is achieved, but fabrication cost increases and integration density decreases
Solution Approach 1:
The patent combines both low-voltage and high-voltage MOS devices on a single semiconductor substrate, merging previously separate integrated circuits into one unified structure. This integration directly reduces fabrication costs by eliminating the need to manufacture and assemble separate circuits while maintaining full device functionality.
Solution Approach 2:
The semiconductor substrate is designed to serve multiple functions simultaneously, supporting both low-voltage and high-voltage device operations. The universal substrate structure accommodates different voltage requirements through specialized device regions, achieving multi-functionality without requiring separate dedicated substrates.
2Adaptability or versatility
If separate integrated circuits are used for low-voltage and high-voltage devices, then device functionality is achieved, but integration density decreases
Solution Approach 1:
By merging low-voltage and high-voltage devices onto one substrate, the patent achieves higher integration density compared to using separate circuits. The combined structure allows for optimized spatial arrangement and reduced overall area while preserving all required device functionalities.
3Ease of manufacture
If conventional photomask and lithography processes are used, then device fabrication is achieved, but the number of processes increases
Solution Approach 1:
The patent employs a universal photomask design that serves multiple fabrication purposes simultaneously. The same photomask and lithography process structure is used for forming both low-voltage and high-voltage devices, reducing the total number of required photomasks and processing steps while achieving complete device fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of both low-voltage and high-voltage MOS devices on a common substrate, reducing fabrication costs and increasing integration density while allowing for adjustable channel and drift regions without altering doping concentrations or photomask designs.
Implementation Method 1
a first light-doping region in a substrate, and the conductive type of the first light-doping region is similar to that of the substrate
Implementation Method 2
A first well is disposed in the substrate to substantially contact a side of the first light-doping region without extending under the first light-doping region, wherein the conductive type of the first well is opposite that of the first light-doping region
Implementation Method 3
A first gate stack is disposed on a part of the first light-doping region and a part of the first well
Implementation Method 4
A plurality of first heavy-doping regions are disposed in the first well and the first light-doping region at two sides of the first gate stack
Data Source
AI summary
A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.