Integrated HV MOS and Bipolar Junction ESD Protection
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Solution Overview
Problem
High-voltage electrostatic discharge (ESD) protection devices face challenges in achieving good ESD performance due to higher current density and electric field at surface junction regions, leading to potential physical damage, and require additional external ESD detection circuits to reduce trigger voltage, which can result in latch-up during normal operation.
Innovation Solution
A semiconductor device design incorporating a high-voltage (HV) metal-on-semiconductor (MOS) structure, a low-voltage (LV) MOS structure, and a bipolar junction (BJ) structure formed in the substrate, where the HV and LV MOS structures share common semiconductor regions, eliminating the need for additional wiring and reducing device size, and integrating a BJ structure to enhance ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device size is reduced, then the surface-bulk ratio increases and surface area has larger impact on performance, but obtaining good ESD performance becomes more challenging
Solution Approach 1:
The patent combines HV and LV MOS structures to share common semiconductor regions (drain region, body region, source region), creating an integrated device that achieves both small size and good ESD performance through functional merging rather than separate components
Solution Approach 2:
The patent implements multi-functional semiconductor regions where the same physical regions serve multiple purposes: the drain region serves as drain for both HV and LV MOS, the body region serves as body for both MOS structures and collector for BJ, and the source region serves as source for both MOS structures. This universal usage reduces device size while maintaining ESD performance
2Temperature
If the operation voltage increases, then the breakdown voltage requirement increases, but on-chip ESD protection design becomes more challenging
Solution Approach 1:
The patent merges HV MOS, LV MOS, and BJ structures into a single integrated device, eliminating the need for additional external ESD detection circuits and simplifying the design of high-voltage ESD protection
Solution Approach 2:
The patent creates multi-functional structures where semiconductor regions serve multiple voltage levels and functions simultaneously, enabling the device to handle high breakdown voltage requirements while maintaining simple on-chip ESD protection design
3Reliability
If the on-state resistance is reduced, then ESD current concentrates near the surface or drain, but this results in higher current density and electric field at surface junction regions causing physical damage
Solution Approach 1:
The patent combines HV MOS with BJ structure where the bipolar junction provides alternative current path through the base and collector regions, distributing ESD current away from surface junction regions and reducing peak current density while maintaining low on-state resistance
Solution Approach 2:
The patent implements multi-functional semiconductor regions where the drain region serves as drain electrode for HV MOS and base for BJ, and the body region serves as body for HV MOS and collector for BJ. This universal usage creates multiple current paths that distribute ESD current and reduce concentration at surface junctions
4Reliability
If the trigger voltage is reduced, then ESD protection activates earlier, but additional external ESD detection circuits are needed which increases device complexity
Solution Approach 1:
The patent integrates the ESD detection function directly into the HV MOS structure by sharing semiconductor regions, eliminating the need for separate external ESD detection circuits and reducing device complexity while maintaining low trigger voltage
Solution Approach 2:
The patent creates multi-functional structures where the HV MOS structure serves both as the protection device and as the ESD detection mechanism, with shared drain and body regions providing both protection function and trigger detection capability
5Reliability
If the holding voltage is reduced, then the device is more sensitive to voltage changes, but this results in latch-up during normal operation from unwanted noise or voltage spikes
Solution Approach 1:
The patent combines HV MOS with LV MOS structure where the LV MOS provides stable reference and the shared source region creates a stable common potential, reducing susceptibility to latch-up from voltage spikes while maintaining appropriate holding voltage
Data Source
AI summary
A semiconductor device includes first metal-on-semiconductor (MOS), second MOS, and bipolar junction (BJ) structures formed in a substrate. The first MOS structure includes first drain, first channel, and first source regions arranged along a first direction. The first MOS structure further includes a drain electrode formed over and conductively coupled to the first drain region, and a body region formed below and conductively coupled to the channel region. The second MOS structure includes second drain, second channel, and second source regions arranged along a second direction different from the first direction. The BJ structure includes emitter, base, and collector regions. The first source region and the second drain region share a first common semiconductor region in the substrate. The drain electrode and the base region share a second common semiconductor region in the substrate. The body region and the collector region share a third common semiconductor region in the substrate.