High Voltage MOS Device Gate Dielectric Segmentation
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Solution Overview
Problem
High-voltage MOS devices with thick gate oxide layers suffer from reduced uniformity of shallow source/drain junctions and increased variation in breakdown voltage due to the thick gate oxide layer, affecting the reliability of the devices.
Innovation Solution
A method is introduced where a portion of the thick gate dielectric layer is removed before forming the source/drain regions, allowing ion implantation to occur without passing through the thick layer, thereby improving the uniformity of the shallow source/drain junction and reducing the breakdown voltage variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thick gate oxide layer is used for high-voltage operations, then the device can operate at high voltage, but the uniformity of the shallow source/drain junction formed by ion implantation through the gate oxide layer is reduced
Solution Approach 1:
The gate dielectric layer is segmented into two distinct regions: a thick gate dielectric layer in the channel region for high-voltage operation, and a thin gate dielectric layer in the source/drain region for uniform ion implantation. This segmentation allows each region to have optimized thickness for its specific function, resolving the contradiction between high-voltage capability and implantation uniformity.
Solution Approach 2:
Different regions of the gate dielectric layer are given different local qualities (thicknesses) to satisfy different functional requirements. The thick region provides high-voltage breakdown capability while the thin region enables uniform ion implantation for source/drain junction formation. This local differentiation resolves the contradiction by allowing each area to be optimized for its specific purpose.
2Strength
If a thick gate oxide layer is used for high-voltage operations, then the device can withstand high voltage, but the variation of breakdown voltage of the HV device is large
Solution Approach 1:
The gate dielectric layer is divided into thick and thin regions, where the thick region maintains high breakdown voltage capability while the thin region ensures uniform ion implantation. This segmentation reduces breakdown voltage variation by eliminating the implantation non-uniformity caused by the thick layer, while preserving the high-voltage capability through the thick channel region.
Solution Approach 2:
By providing different local qualities (thicknesses) of the gate dielectric layer in different regions, the invention achieves both high breakdown voltage capability (through the thick channel region) and reduced breakdown voltage variation (through the thin source/drain region that enables uniform implantation).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of the shallow source/drain junction and reduces the variation in breakdown voltage of high-voltage MOS devices, improving their operational reliability.
Implementation Method 1
the shallow source/drain (S/D) junction formed by ion implantation through the gate oxide layer
Data Source
AI summary
A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.