HV MOS Transistor Sub-Gate Structure for GIDL Leakage Reduction

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Solution Overview

Problem

Conventional DMOS transistor devices experience increased leakage current due to the gate-induced drain leakage (GIDL) effect as sidewall spacers thin, particularly in high-voltage applications, where the heavier doped source/drain regions under the poly gate exacerbate this issue.

Innovation Solution

A manufacturing method for a high-voltage metal-oxide-semiconductor (HV MOS) transistor device involves forming a sub-gate structure separated from the gate structure and electrically connecting it to the drain region via a contact structure, eliminating the electric potential difference and thereby reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sidewall spacers are made thinner in advanced process nodes, then device integration density is improved, but leakage current increases due to the GIDL effect

Engineering Contradiction:
Improvedevice integration densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into a main gate and a sub-gate structure. The sub-gate is positioned adjacent to the drain region and electrically connected to it, creating a localized potential control zone that suppresses the GIDL effect at the drain-gate interface without requiring thicker sidewall spacers elsewhere in the device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sub-gate structure is electrically connected to the drain region through a contact structure, establishing an equipotential relationship between the sub-gate and drain. This eliminates the electric potential difference that would otherwise exist between these regions, thereby suppressing the GIDL effect and reducing leakage current.

Inventive Principle:
Principle #12Equipotentiality

2Reliability

If heavier doped source/drain regions are used under the poly gate, then on-current is improved, but leakage current increases due to the GIDL effect

Engineering Contradiction:
Improveon-currentVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The sub-gate structure is specifically positioned adjacent to the drain region where the GIDL effect occurs, rather than uniformly modifying the entire gate structure. This localized approach allows the heavier doped source/drain regions to maintain their beneficial on-current enhancement while the sub-gate selectively suppresses leakage at the critical drain-gate interface.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The sub-gate structure acts as an intermediary element between the main gate and the drain region. It provides localized potential control at the drain-gate interface, mediating the interaction between the heavily doped drain region and the main gate to suppress the GIDL effect while preserving the benefits of heavy doping for on-current.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces leakage current from the drain region to the bulk region, improving the operational efficiency of HV MOS transistor devices by suppressing the GIDL effect.

Implementation Method 1

leakage current (Ioff) of the DMOS will rise quickly because of the gate induced drain leakage (GIDL) effect

Methodology Applied
Scientific EffectGate induced drain leakage (GIDL) effect: Electric Field

Data Source

PatentUS9722072B2Manufacturing method of high-voltage metal-oxide-semiconductor transistor
Publication Date: 2017.08.01 UNITED MICROELECTRONICS CORP
  • US9722072B2 patent drawing
  • US9722072B2 patent drawing
  • US9722072B2 patent drawing

AI summary

A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.