HV-MV-LV Transistor Integration With Aligned Gate and Fin Surfaces
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-voltage, medium-voltage, and low-voltage transistors due to issues such as current leakage and breakdown voltage control, particularly as device scaling decreases.
Innovation Solution
A method for fabricating semiconductor devices that includes defining high-voltage, medium-voltage, and low-voltage regions on a substrate, forming specific transistor structures with fin-shaped structures and gate dielectric layers, and using a combination of processes like sidewall image transfer, chemical vapor deposition, and rapid thermal oxidation to create doped regions and gate electrodes, ensuring even top surfaces and effective current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-voltage devices and FinFET devices are integrated on the same chip, then power switching efficiency is improved and energy loss is decreased, but current leakage and breakdown voltage control become more difficult
Solution Approach 1:
The chip is divided into distinct high-voltage device regions and FinFET device regions with separate fabrication processes. The high-voltage devices (VDMOS, IGBT, LDMOS) are fabricated first, then the FinFET devices are fabricated in separate regions using additional processing steps, allowing each device type to be optimized independently while coexisting on the same chip
Solution Approach 2:
Different gate dielectric layer structures are used in different regions: thick gate dielectric layers (50-200 nm) are used in high-voltage device regions to prevent breakdown and control leakage, while thin gate dielectric layers (2-10 nm) are used in FinFET regions to enable effective channel control and high switching efficiency, with each region having locally optimized properties
2Productivity
If device scaling is continued to decrease size, then integration density is improved, but current leakage and breakdown voltage control deteriorate
Solution Approach 1:
The patent transitions from planar MOS transistor structures to three-dimensional FinFET structures, where the gate wraps around the fin-shaped silicon substrate on three sides. This vertical dimension provides superior electrostatic control over the channel, enabling effective breakdown voltage control and reduced leakage even as device dimensions are scaled down, while maintaining high integration density
3Strength
If thick gate dielectric layer is used in high-voltage region, then breakdown voltage is improved, but top surface evenness with fin structure deteriorates
Solution Approach 1:
The gate dielectric layer is formed to a predetermined thickness that extends beyond the fin structure in advance, before the gate electrode is formed. This preliminary extension ensures that when the gate electrode is deposited and patterned, the gate dielectric layer already provides the necessary even top surface alignment with the fin structure, preventing subsequent processing issues while maintaining the required thickness for high breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by improving current control and breakdown voltage management across different voltage regions, reducing leakage and increasing efficiency in power switching operations.
Implementation Method 1
a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer
Implementation Method 2
forming specific transistor structures with fin-shaped structures and gate dielectric layers, and using a combination of processes like sidewall image transfer, chemical vapor deposition, and rapid thermal oxidation to create doped regions
Data Source
AI summary
A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.