HV-MV Semiconductor Trench Isolation for Leakage Control
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-voltage and FinFET devices due to issues such as current leakage and control of breakdown voltage as the scale of devices continues to decrease, necessitating improved fabrication methods for enhanced performance.
Innovation Solution
A method for fabricating semiconductor devices involves creating a substrate with high-voltage and medium-voltage regions, forming specific trench structures and shallow trench isolations, and constructing gate structures with varying dielectric layer thicknesses to improve control and efficiency, including the use of fin-shaped structures and epitaxial layers to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage devices and FinFET devices are integrated on the same chip, then device functionality and power efficiency are improved, but current leakage and breakdown voltage control become more difficult
Solution Approach 1:
The substrate is divided into distinct high-voltage regions and low-voltage regions with different trench isolation structures. HV regions use deep trenches extending to the substrate bottom with first STI, while LV regions use shallower trenches with second STI. This segmentation allows each region to be optimized independently, preventing current leakage between regions while maintaining high-level integration.
Solution Approach 2:
Different trench isolation structures are applied to different regions based on their voltage requirements. The first STI in HV regions has different characteristics (deeper trenches, different fill materials) compared to the second STI in LV regions. This local quality approach ensures each region has the precise electrical properties needed, solving the breakdown voltage control issue while maintaining integration.
2Area of stationary object
If device scale is reduced to increase integration density, then chip area is reduced, but current leakage and breakdown voltage control deteriorate
Solution Approach 1:
Instead of relying solely on planar dimensions for isolation, the patent introduces vertical dimensionality through deep trenches that extend to the substrate bottom in HV regions. This third dimension provides effective electrical isolation even when lateral dimensions are reduced for higher integration density, maintaining breakdown voltage control despite smaller chip area.
Solution Approach 2:
The trench isolation structures are nested within the substrate, with the first STI deeply embedded in HV regions and the second STI in LV regions. This nesting approach allows compact integration of multiple voltage domains within a small area while maintaining proper electrical isolation and breakdown voltage control through the vertically-oriented isolation structures.
3Reliability
If deep trenches are formed in high-voltage regions, then breakdown voltage control is improved, but manufacturing complexity increases
Solution Approach 1:
The deep trenches for first STI are formed in HV regions before the shallower trenches for second STI are formed in LV regions. This preliminary action allows the complex deep trench formation to be completed first when the substrate is most accessible, simplifying subsequent processing steps and reducing overall manufacturing complexity while maintaining effective breakdown voltage control.
Solution Approach 2:
The manufacturing process is made dynamic through selective trench formation at different stages. The first STI trenches are formed and filled first in HV regions, then the second STI trenches are formed and filled in LV regions. This dynamic, staged approach manages manufacturing complexity by breaking down the complex multi-region isolation into manageable sequential steps rather than attempting simultaneous formation.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.