High-Voltage Regulator Cascode Circuit for Low Bias Current
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Solution Overview
Problem
High voltage regulators for NAND flash memory devices face challenges in minimizing DC bias current while maintaining efficiency, as increasing the resistance value to reduce current consumption leads to area penalties and parasitic increases, and existing solutions do not effectively manage current flow without expanding the regulator's size.
Innovation Solution
A high voltage linear regulator design incorporating a current mirror and cascode block that reduces second stage current without increasing area, using high voltage PMOS transistors with low breakdown voltage, and includes a precharge transistor and Miller compensation capacitor to manage voltage levels and feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the resistance value is increased to reduce current consumption, then DC bias current is minimized, but area increases and parasitic increases
Solution Approach 1:
The regulator is divided into multiple stages: a first stage with an operational amplifier for voltage amplification, a second stage with a common source configuration including transistors M3 and MOUT, and a third stage with source follower configuration. This segmentation allows current reduction in the second stage without requiring a single large resistor, thus reducing area while minimizing DC bias current.
Solution Approach 2:
The patent changes the configuration from a simple high-value resistor to a multi-stage transistor-based circuit. By adjusting the parameters of transistors M3 and MOUT (such as their width-to-length ratios and threshold voltages), the circuit achieves low current consumption without requiring large physical area, resolving the contradiction between current minimization and area reduction.
2Use of energy by moving object
If the resistance value is increased to reduce current consumption, then DC bias current is minimized, but parasitic increases
Solution Approach 1:
The circuit is segmented into multiple active stages that collectively replace the function of a single large resistor. The operational amplifier in the first stage and the transistor pair in the second stage work together to achieve current control without relying on a large resistance value, thereby reducing parasitic effects associated with high-value resistors.
Solution Approach 2:
The patent substitutes the passive resistor-based current control mechanism with an active transistor-based control system. The transistors M3 and MOUT, controlled by the operational amplifier, dynamically regulate current flow, replacing the static resistor approach and reducing parasitic inductance and capacitance associated with high-value resistors.
3Device complexity
If high voltage PMOS transistors with low breakdown voltage are used, then device complexity is reduced, but transistor breakdown risk increases
Solution Approach 1:
The patent introduces an intermediary protection mechanism where the gate of transistor M3 is controlled by the operational amplifier output, and the gate of transistor MOUT is controlled by the drain of M3. This intermediary control structure ensures that the voltage across each transistor remains within safe limits, preventing breakdown while using simple PMOS transistors with low breakdown voltage.
Solution Approach 2:
The operational amplifier provides feedback control to regulate the gate voltages of transistors M3 and MOUT. By monitoring the voltage conditions and adjusting the gate signals accordingly, the feedback mechanism prevents excessive voltage stress on the PMOS transistors, ensuring reliable operation without requiring complex high-breakdown-voltage devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes DC bias current, maintains efficiency, and prevents transistor breakdown, allowing for fast startup and output drop recovery while maintaining a compact regulator size.
Implementation Method 1
a mirror circuit forming two current paths between an internal node and ground, and between the internal node and a second intermediate output node of the regulator
Implementation Method 2
Miller compensation capacitor to manage voltage levels and feedback
Implementation Method 3
an operational amplifier OPAMP for receiving a reference voltage VREF and a feedback voltage VFEEDBACK to output a voltage amplifying the difference of the reference voltage VREF and the feedback voltage VFEEDBACK
Implementation Method 4
cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node
Data Source
AI summary
Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.