HV IC Testing Assembly with Smooth Electrodes
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Solution Overview
Problem
High voltage (HV) IC testing inaccuracies occur due to non-negligible charge detection, which may be caused by design and test vulnerabilities such as partial discharge or arcing, rather than internal IC breakdown, often resulting from the geometry and material properties of the FR-4 test boards used in prior art approaches.
Innovation Solution
The development of a high voltage integrated circuit testing assembly featuring a slab with smooth, surface-discontinuity-free electrodes and a vertical charge separation wall to reduce the likelihood of partial discharge or arcing, utilizing materials like PEEK or DELRIN for the slab and incorporating a two-piece UHV contactor shim for precise IC alignment and compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrodes are etched on FR-4 test board, then electrode geometry can be varied, but surface discontinuities and edge shapes create higher electric field density leading to partial discharge and arcing
Solution Approach 1:
The patent changes the surface geometry parameter of electrodes from etched profiles with sharp edges to smooth, continuous surfaces. This parameter change eliminates surface discontinuities that concentrate electric field, thereby preventing partial discharge and arcing while maintaining manufacturing feasibility through alternative fabrication methods.
Solution Approach 2:
The patent employs composite construction by affixing electrodes to a non-conductive slab, creating a composite structure that combines the electrical functionality of metal electrodes with the insulating properties of the slab material. This composite approach allows for smooth electrode surfaces without the edge effects inherent in etched FR-4 boards.
2Measurement precision
If high voltage is applied between test electrodes, then IC isolation performance can be evaluated, but charge accumulation and arcing occur causing false failure detection
Solution Approach 1:
The patent modifies the electric field distribution parameter by eliminating surface discontinuities and sharp edges on electrodes. This parameter change prevents field concentration that would otherwise cause partial discharge and arcing, enabling accurate measurement of IC isolation performance without false failures from charge accumulation.
3Shape
If etch duration is increased to modify electrode shape, then electrode geometry changes, but electric field density increases at edges creating corona discharge
Solution Approach 1:
The patent fundamentally changes the electrode surface parameter from etched geometries with varying edge sharpness to uniformly smooth surfaces. This parameter change eliminates the correlation between etch duration and harmful edge effects, as smooth surfaces prevent field concentration regardless of specific geometric variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the occurrence of false fails during HV testing by minimizing charge accumulation and arcing between electrodes, allowing for more accurate assessment of IC isolation performance without unnecessary voltage-induced errors.
Implementation Method 1
the first electrode has a first major axis parallel to the slab axis, is coupled to receive a first voltage for coupling to a first set of pins on an integrated circuit, and includes a first surface area facing the slab axis, wherein the first surface area does not include a surface discontinuity. The second electrode has a second major axis parallel to the slab axis, is coupled to receive a second voltage
Data Source
AI summary
An integrated circuit testing assembly, comprising a slab having a slab axis, and a first electrode and second electrode affixed relative to the slab. The first electrode has a first major axis parallel to the slab axis, is coupled to receive a first voltage for coupling to a first set of pins on an integrated circuit, and includes a first surface area facing the slab axis, wherein the first surface area does not include a surface discontinuity. The second electrode has a second major axis parallel to the slab axis, is coupled to receive a second voltage for coupling to second first set of pins on an integrated circuit, and includes a second surface area facing the slab axis, wherein the second surface area does not include a surface discontinuity.