High Voltage Transistor ESD Protection via Parasitic Circuit
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Solution Overview
Problem
Conventional high voltage devices fail to provide effective electrostatic discharge (ESD) protection, allowing large currents from ESD events to flow through internal circuits and potentially damaging electronic apparatus.
Innovation Solution
Integration of a high voltage transistor with a protection device, such as a MOSFET or bipolar junction transistor, that includes a parasitical equivalent circuit and heavily doped layers to direct ESD currents safely to ground, enhancing ESD protection without affecting the device's operational capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage device is used to process high voltages, then the device can sustain high voltage conditions, but it cannot provide effective ESD protection and large ESD currents may damage internal circuits
Solution Approach 1:
The patent introduces a protection device as an intermediary component between the high voltage transistor and ground. This protection device includes a parasitical equivalent circuit that acts as a mediator to safely divert ESD currents away from internal circuits. The protection device is coupled to the second end of the high voltage transistor and provides a controlled path for ESD current dissipation, preventing direct damage to sensitive internal components.
Solution Approach 2:
The patent segments the ESD protection function from the high voltage processing function by introducing a separate protection device with parasitical equivalent circuit. This segmentation allows the high voltage transistor to focus on voltage processing while the protection device专门 handles ESD current management. The parasitical equivalent circuit is further segmented into specific components that can be independently optimized for ESD protection.
2Reliability
If a protection device with parasitical equivalent circuit is added to the high voltage device, then ESD protection capability is enhanced, but the device complexity increases
Solution Approach 1:
The patent merges the protection device with the high voltage transistor by coupling them in an integrated manner. The protection device is directly coupled to the second end of the high voltage transistor, and both devices share common structural elements and fabrication processes. This merging approach allows ESD protection functionality to be added without requiring completely separate discrete components, thereby limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances ESD protection capabilities, maintaining the original operational characteristics and layout area of the circuit while significantly increasing the breakdown voltage and ESD current handling capacity, as demonstrated by simulation and test data.
Implementation Method 1
When the voltage input/output terminal is charged according to positive electrostatic discharge charges, a current corresponding to the positive electrostatic discharge charges flows from the voltage input/output terminal through the high voltage transistor and the equivalent circuit in the protection device toward the ground terminal
Data Source
AI summary
A high voltage device includes a high voltage transistor and a protection device. The high voltage transistor has a first end and a second end, in which the first end is coupled to a voltage input/output terminal. The protection device is coupled between the second end of the high voltage transistor and a ground terminal, and has a parasitical equivalent circuit. When the voltage input/output terminal is charged based on positive ESD charges, the current corresponding to the positive ESD charges flows from the voltage input/output terminal through the high voltage transistor and the equivalent circuit in the protection device toward the ground terminal. A power management circuit is also disclosed herein.