High Voltage Transistor Gate Edge Field Oxide Design
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Solution Overview
Problem
Conventional high voltage transistors face challenges in achieving high breakdown voltage while minimizing hot carriers and electric field intensity at the edge portions, which leads to increased current leakage and reduced integration capabilities due to the high electric field intensity at the corner of the drain.
Innovation Solution
A high voltage transistor design incorporating a thermal oxide pattern and a chemical vapor deposition (CVD) oxide pattern, where the edge portion of the gate electrode is composed of thermal oxide, reducing electric field intensity and minimizing hot carriers, and the gate oxide layer includes both thermal and CVD oxide patterns to enhance current and on-resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to achieve high breakdown voltage, then the breakdown voltage increases, but the integration density decreases and the device area increases
Solution Approach 1:
The patent applies local quality by forming a field oxide layer specifically at the corner portion of the drain region where electric field intensity is highest. This localized oxidation approach targets the specific area needing field control without requiring overall device scaling, thus maintaining high breakdown voltage while avoiding increased device area.
Solution Approach 2:
The patent changes the physical parameter of the oxide layer by using thermal oxidation to create a field oxide layer with different properties than the gate oxide layer. The field oxide layer has higher dielectric strength and is specifically positioned to control the electric field at the drain corner, enabling high breakdown voltage without proportionally increasing device dimensions.
2Object-generated harmful factors
If the electric field intensity at the drain corner is reduced to minimize hot carriers, then hot carrier generation decreases, but the current leakage increases
Solution Approach 1:
The patent applies local quality by forming a field oxide layer specifically at the corner portion of the drain region where electric field intensity is highest. This localized oxidation approach targets the specific area needing field control without requiring overall device scaling, thus maintaining high breakdown voltage while avoiding increased device area.
Solution Approach 2:
The field oxide layer acts as an intermediary structure between the high-field drain corner and the channel region. It provides gradual field control and prevents direct field enhancement at the corner, thereby reducing hot carrier generation while maintaining proper current blocking through the pinned-off channel.
3Ease of manufacture
If a single oxide layer is used for the gate oxide, then the manufacturing process is simplified, but the current and on-resistance characteristics are suboptimal
Solution Approach 1:
The patent segments the oxide layer into two distinct parts: a gate oxide layer formed by CVD for optimal electrical characteristics, and a field oxide layer formed by thermal oxidation for field control. This segmentation allows each layer to be optimized for its specific function while maintaining manufacturing feasibility through sequential formation processes.
Solution Approach 2:
The patent uses composite materials by combining two different oxide layers with distinct formation methods and properties. The CVD gate oxide provides excellent electrical characteristics for low on-resistance, while the thermally grown field oxide provides superior dielectric strength for current blocking, creating a composite oxide structure that optimizes both current and resistance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces electric field intensity at the edge of the gate electrode, increases breakdown voltage, and improves current and on-resistance characteristics, preventing hot carriers and electrical shorts, even under high voltage applications.
Implementation Method 1
an edge portion of a gate electrode of a high voltage transistor is comprised of a thermal oxide, and thus an electric field intensity is sufficiently reduced at the edge portion of the gate electrode
Implementation Method 2
a chemical vapor deposition (CVD) oxide pattern covering the thermal oxide pattern and the substrate
Data Source
AI summary
In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation pattern is covered with the second insulation pattern. A gate electrode including a first end portion and a second end portion opposite to the first end portion is formed on the substrate by depositing conductive materials onto the substrate. The first end portion is formed on the first insulation pattern and the second end portion is formed on the second insulation pattern. Source/drain regions are formed at surface portions of the substrate by implanting impurities onto the substrate. Electric field intensity at an edge portion of the gate electrode is reduced, and the HV transistor has a high breakdown voltage.