High-Voltage Transistor Isolation Layout for Breakdown Voltage
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Solution Overview
Problem
High-voltage transistors require enhanced breakdown voltage to withstand increasing operational voltages, but existing manufacturing processes for LDMOS transistors fail to meet these requirements without compromising compatibility with medium-voltage or low-voltage transistors.
Innovation Solution
A method of forming semiconductor structures with high-voltage transistors and non-high-voltage transistors, where isolation regions subjected to different working voltages are formed using distinct methods and structures, thereby improving the voltage-withstanding capability of high-voltage transistors while maintaining manufacturing compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform formation process is applied for all isolation regions of LDMOS transistors, then manufacturing compatibility is maintained, but the breakdown voltage requirement for high-voltage transistors cannot be met
Solution Approach 1:
The patent applies different formation processes to different isolation regions based on their specific voltage requirements. High-voltage transistor isolation regions undergo a first formation process (including trench isolation with specific depth and filling material), while medium-voltage and low-voltage transistor isolation regions undergo a second formation process. This local differentiation allows each region to be optimized for its operational requirements while maintaining overall manufacturing compatibility through selective application of processes.
Solution Approach 2:
The patent segments the isolation regions into different categories based on voltage requirements. The substrate is divided into high-voltage regions and non-high-voltage regions, with each segment receiving tailored formation processes. This segmentation enables the high-voltage isolation regions to achieve enhanced breakdown voltage through deeper trenches and specialized filling, while other regions continue with standard processes, thus resolving the contradiction between reliability and manufacturing ease.
2Reliability
If the breakdown voltage is enhanced for high-voltage transistors, then voltage-withstanding capability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming high-voltage isolation regions with enhanced characteristics (deeper trenches, specific filling materials) before subsequent manufacturing steps. The trench isolation structures are prepared in advance with appropriate depth and filling to ensure high-voltage capability is established early in the process flow. This preliminary preparation allows later steps to proceed with standard processes, reducing overall complexity while maintaining enhanced voltage-withstanding capability.
Solution Approach 2:
The patent applies complex formation processes only locally to high-voltage isolation regions where they are truly needed, rather than uniformly across all regions. The first formation process (with deeper trenches and specialized filling) is selectively applied only to high-voltage transistor regions, while medium-voltage and low-voltage regions receive simpler second formation processes. This localized application of complexity minimizes the overall impact on manufacturing process complexity while achieving the required voltage-withstanding capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method enhances the voltage-withstanding capability of high-voltage transistors, ensuring they can operate effectively at higher voltages without compromising the production compatibility with other voltage-level transistors, thus improving overall semiconductor production efficiency and cost-effectiveness.
Implementation Method 1
performing an ion implantation operation on the substrate through the opening to form an implant region in the substrate
Implementation Method 2
performing a thermal operation on the substrate to form a first isolation region, spaced apart from the barrier layer, from the implant region
Data Source
AI summary
A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.