HVAC Controller Reset Source Detection Using POR And Reset Codes

The patent segments the reset detection functionality by dividing the non-volatile memory into multiple distinct sections (first reset code section and second reset code section) and using separate registers (POR register, watchdog reset register) to track different reset sources. This segmentation allows the controller to independently monitor and identify the specific source of each reset event, thereby improving measurement precision without requiring a complete redesign of the controller architecture.

The patent introduces intermediary elements (POR register, watchdog reset register, and reset code sections in non-volatile memory) that act as mediators between the reset generation mechanisms and the processor. These intermediaries capture and store reset information in a structured manner, enabling the processor to accurately deduce the reset source without directly interfacing with each individual reset mechanism, thus balancing precision improvement with acceptable device complexity.

The patent applies universality by designing the non-volatile memory to serve multiple functions: it stores both the first and second reset codes, and can be selectively updated based on the reset source. The processor universally handles different reset scenarios (POR, watchdog, scheduled) using a unified deduction algorithm that checks the same registers and memory sections, thereby improving reset source differentiation while avoiding the need for entirely separate tracking systems for each reset type.

The patent implements preliminary action by pre-structuring the non-volatile memory with designated first and second reset code sections before operation begins. This preliminary organization allows the controller to immediately and accurately identify reset sources without requiring complex real-time analysis, as the memory structure is already optimized for rapid reset source deduction from the moment the system starts operating.

The patent implements feedback mechanisms where the POR register and watchdog reset register continuously reflect the current reset state, and the processor regularly checks these registers along with the reset code sections in non-volatile memory. This feedback loop provides the processor with up-to-date information about reset conditions, enabling efficient troubleshooting through systematic analysis of predefined register states and memory contents, thereby improving productivity while managing detection difficulty through structured feedback.

The controller performs self-service by automatically analyzing its own reset conditions through the processor examining the POR register, watchdog reset register, and reset code sections. This self-diagnostic capability eliminates the need for external intervention to identify reset sources, allowing the system to automatically determine the reset cause and provide this information for troubleshooting, thereby improving productivity without proportionally increasing the difficulty of detection for end users.