HVFET Drain Region Segmentation for Low ON Resistance

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Solution Overview

Problem

High-voltage field-effect transistors (HVFETs) face challenges in maintaining high breakdown voltages and low ON resistance to minimize conduction losses in power conversion circuits, particularly due to the high voltages and currents they are subjected to.

Innovation Solution

The fabrication of HVFETs involves forming a drain region with stacked p-doped implanted layers using ion implantation through a thin oxide layer, which aids in creating a gaussian distribution doping profile, and the use of a gate oxide layer and thick oxide layer to form a channel region, along with a substrate that includes a drain, body, and source region, to manage voltage and current effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If HVFETs are designed to have high breakdown voltages to withstand high voltages during operation, then the device can operate at high voltages (700-800 V), but the ON resistance increases leading to higher conduction losses

Engineering Contradiction:
Improvebreakdown voltageVSAvoidconduction losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The drain region is segmented into multiple implanted layers (first, second, and third implanted layers) with different doping concentrations and depths. This segmentation allows each layer to contribute differently to the electrical characteristics, enabling the device to achieve both high breakdown voltage and low ON resistance by optimizing the profile of each segment independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the drain are given different doping qualities through the implanted layers. The first implanted layer has a first doping concentration, the second has a second doping concentration, and the third has a third doping concentration. This local variation in doping quality allows the device to maintain high breakdown voltage in certain regions while achieving low ON resistance in others, thereby reducing conduction losses.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If ion implantation is performed through a thin oxide layer to create gaussian distribution doping profile, then the doping precision is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improvedoping profile precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A thin oxide layer is formed on the semiconductor substrate before the ion implantation process. This preliminary action of forming the oxide layer serves as a protective and controlling medium during implantation, enabling precise formation of gaussian distribution doping profiles. The oxide layer is later removed after serving its purpose, having already achieved the desired precision in dopant placement.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables HVFETs to operate efficiently with high breakdown voltages and low ON resistance, reducing conduction losses and enhancing performance in power conversion circuits.

Implementation Method 1

The fabrication of HVFETs involves forming a drain region with stacked p-doped implanted layers using ion implantation through a thin oxide layer, which aids in creating a gaussian distribution doping profile

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9660053B2High-voltage field-effect transistor having multiple implanted layers
Publication Date: 2017.05.23 POWER INTEGRATIONS INC
  • US9660053B2 patent drawing
  • US9660053B2 patent drawing
  • US9660053B2 patent drawing

AI summary

A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.