HVL-Based ATE Test Pattern Generation for Faster IC Simulation
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Solution Overview
Problem
Existing methods for generating integrated circuit test patterns are inefficient and time-consuming, particularly when simulating millions or billions of devices, due to the lengthy simulation of structural circuit models.
Innovation Solution
The use of a Hardware Verification Language (HVL) model that simulates the response of the integrated circuit obliviously to its circuitry, combined with a simulation program and translation program to generate ATE testing patterns, allowing for rapid test pattern generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If structural circuit models are used for simulation, then test pattern generation is comprehensive and accurate, but simulation time becomes excessively long
Solution Approach 1:
The patent creates a behavioral model that copies only the essential input-output functionality of the circuit under test, rather than replicating the complete structural circuit model. This behavioral copy captures the necessary test characteristics while eliminating unnecessary structural details, achieving rapid simulation without sacrificing test pattern effectiveness
Solution Approach 2:
The invention extracts and isolates the critical behavioral characteristics of the circuit from its complete structural model. By taking out only the essential input-output relationships and test-relevant behaviors, the system achieves fast simulation while maintaining comprehensive test coverage for the extracted behavioral aspects
2Reliability
If millions or billions of devices are simulated, then test coverage is improved, but generation time increases significantly
Solution Approach 1:
The behavioral model serves as a simplified copy that can be instantiated and simulated rapidly for large numbers of devices. Each device simulation uses the same compact behavioral representation, enabling efficient batch processing of millions or billions of devices while maintaining consistent test coverage across all instances
Solution Approach 2:
The patent changes the fundamental parameters of the simulation model from detailed structural parameters to abstract behavioral parameters. This parameter transformation allows the simulation to process devices at a higher level of abstraction, dramatically increasing throughput while maintaining the ability to generate comprehensive test patterns through the behavioral specifications
Data Source
AI summary
An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a high-level verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one DUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.