HV-LDMOS Transistor Gate Penetrating Shallow Trench Isolation
Solution Overview
Problem
High voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) transistor devices face a trade-off between achieving high breakdown voltage and low ON-resistance, with existing designs struggling to optimize both parameters simultaneously.
Innovation Solution
The implementation of a shallow trench isolation (STI) structure with an epitaxial layer and a gate extending into the STI, which forces the current path closer to the edge of the STI, thereby reducing resistance and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDMOS transistor device is designed to achieve high breakdown voltage, then the drift region area is increased, but the ON-resistance increases accordingly
Solution Approach 1:
The gate structure is extended into the third dimension by penetrating into the STI region, creating a vertical component in addition to the horizontal gate length. This dimensional extension allows the gate to exert control over a larger effective area without increasing the planar drift region area, thereby achieving high breakdown voltage while maintaining low ON-resistance
Solution Approach 2:
The invention changes the geometric parameters of the gate structure by extending it into the STI region. This parameter change increases the effective gate area and improves the electric field distribution, allowing simultaneous optimization of breakdown voltage and ON-resistance that cannot be achieved with conventional planar gate designs
Data Source
AI summary
A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.