HV-LDMOS Transistor Layout Pattern for Breakdown Voltage and ON-Resistance Trade-off

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Solution Overview

Problem

Conventional high voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) transistor devices face a trade-off between achieving high breakdown voltage and low ON-resistance (RON), as these parameters are conflicting and difficult to optimize simultaneously.

Innovation Solution

The introduction of a non-continuous doped region with gaps between the source and drain regions, featuring complementary conductivity types and varying pattern densities, which reduces the total doped area and enhances breakdown voltage while minimizing RON.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a continuous doped drift region is used to achieve high breakdown voltage, then breakdown voltage is improved, but ON-resistance increases due to large doped area

Engineering Contradiction:
Improvebreakdown voltageVSAvoidON-resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The drift region is segmented into multiple isolated doped regions arranged in a pattern (e.g., interdigitated or mesh structure) rather than a continuous region. This segmentation maintains the necessary electric field distribution for high breakdown voltage while reducing the total doped area, thereby lowering ON-resistance. The gaps between segmented regions allow better electric field control and reduce parasitic effects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the drift structure are given different doping characteristics. The segmented doped regions provide localized high field control where needed, while the gaps between them reduce overall resistance. This local optimization allows simultaneous achievement of high breakdown voltage in critical areas and low ON-resistance in the overall structure.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If the drift region area is increased to reduce ON-resistance, then ON-resistance is improved, but breakdown voltage decreases due to reduced electric field control

Engineering Contradiction:
ImproveON-resistanceVSAvoidbreakdown voltage
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

By segmenting the drift region into a pattern of isolated doped regions, the patent achieves both low ON-resistance (through increased effective area) and high breakdown voltage (through localized electric field control at each segment). The segmented structure allows the drift region to extend over a larger area without sacrificing voltage control capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The drift region is extended into the lateral dimension with a two-dimensional array of segmented doped regions, rather than being confined to a simple one-dimensional structure. This dimensional expansion allows simultaneous optimization of both resistance (area) and breakdown voltage (field control) by distributing doped regions across the device plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If a simple continuous doped structure is used, then manufacturing is simple, but electric field control and breakdown voltage performance are insufficient

Engineering Contradiction:
Improvestructure simplicityVSAvoidbreakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The segmented drift region can be manufactured using standard semiconductor fabrication techniques such as selective ion implantation or diffusion through patterned masks. The segmented pattern is achieved through conventional lithography and doping processes, making the complex structure compatible with existing manufacturing capabilities while significantly improving breakdown voltage performance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8937352B2High voltage metal-oxide-semiconductor transistor device and layout pattern thereof
Publication Date: 2015.01.20 UNITED MICROELECTRONICS CORP
  • US8937352B2 patent drawing
  • US8937352B2 patent drawing
  • US8937352B2 patent drawing

AI summary

A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.