HVMOS Threshold Voltage Uniformity via Fixed Back Gate Lengths
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Solution Overview
Problem
High voltage MOS (HVMOS) transistor devices with varied channel lengths exhibit varying threshold voltages, making memory operations like programming and reading difficult due to the dependence of threshold voltages on channel length.
Innovation Solution
The use of fixed back gate lengths, also referred to as POLY overlaps, and increased gap lengths between back gate and drain extension regions allows for substantially similar threshold voltages across devices with varied channel lengths, enabling the selection of threshold values at minimum channel lengths for use in longer channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If HVMOS devices with varied channel lengths are fabricated using low voltage CMOS devices, then space and cost are saved, but threshold voltages vary making memory operations difficult
Solution Approach 1:
The patent applies local quality by making the back gate length a specific fixed parameter while allowing other dimensions to vary. This localized control of the back gate region creates uniform threshold voltages across devices with different channel lengths, enabling reliable memory operations while maintaining fabrication efficiency.
2Manufacturing precision
If channel length is increased to reduce threshold voltage variation, then threshold uniformity improves, but device area increases
Solution Approach 1:
The patent changes the critical parameter from channel length to back gate length for controlling threshold voltage. By fixing the back gate length while allowing channel length to vary, the invention achieves uniform threshold voltages without increasing device area, as the back gate length is a more effective control parameter for threshold voltage uniformity.
Data Source
AI summary
Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.