HVMOS Transistor Offset Drain Structure for Hot Carrier Injection
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Solution Overview
Problem
Conventional high-voltage metal-oxide-semiconductor (HVMOS) transistor structures face challenges with reduced gaps between the P-N junction and N+ drain region, leading to hot carrier injection (HCI) and degraded time-dependent dielectric breakdown (TDDB) due to dopant diffusion, making them unsuitable for advanced ICs with shrinking device sizes.
Innovation Solution
The HVMOS transistor structure incorporates a first ion well and a second ion well of different conductivity types with a junction interface, a gate overlapping both wells asymmetrically, and a drain region spaced apart from the gate sidewall by an offset distance to prevent dopant diffusion and enhance voltage drop and dielectric breakdown resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gap between the P-N junction and N+ drain region is reduced to accommodate smaller device sizes, then device integration density is improved, but dopant diffusion occurs leading to hot carrier injection and degraded TDDB
Solution Approach 1:
The patent segments the drain region into two distinct parts: a first drain region adjacent to the P-N junction and a second drain region adjacent to the gate. These regions have different doping concentrations, with the first drain region having lower doping to prevent dopant diffusion and the second drain region having higher doping to maintain device performance. This segmentation allows the device to achieve high integration density while maintaining reliability by spatially separating the conflicting requirements.
2Length of moving object
If the gap between the P-N junction and N+ drain region is reduced, then device size is shrunk, but time-dependent dielectric breakdown resistance is degraded due to dopant diffusion
Solution Approach 1:
The patent applies local quality by assigning different doping concentrations to different spatial locations within the drain region. The first drain region near the P-N junction uses lower doping concentration to minimize dopant diffusion and protect the dielectric, while the second drain region near the gate uses higher doping concentration to maintain electrical performance. This localized differentiation allows small device dimensions to coexist with high TDDB resistance.
3Reliability
If highly dosed N-type dopant is used in the N+ drain region, then device conductivity is improved, but dopant diffusion to the gate and P-N junction occurs causing hot carrier injection
Solution Approach 1:
The drain region is segmented into a first drain region with lower doping concentration near the P-N junction and a second drain region with higher doping concentration near the gate. This segmentation allows the device to achieve high conductivity through the heavily doped second region while the lightly doped first region acts as a barrier to dopant diffusion, preventing harmful effects like hot carrier injection.
Solution Approach 2:
The first drain region with lower doping concentration serves as an intermediary layer between the P-N junction and the heavily doped second drain region. This intermediate region with moderate doping concentration acts as a buffer that allows electrical conduction while preventing direct dopant diffusion from the high-dose region to the sensitive P-N junction and gate areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces hot carrier injection and improves time-dependent dielectric breakdown resistance by maintaining the quality of the P-N junction and increasing the voltage drop, making the structure more suitable for advanced ICs.
Implementation Method 1
A highly dosed N-type dopant in the N+ drain region is prone to diffuse the P-N junction 140 and the gate 104 due to the reduced gap between the P-N junction 140 and the N+ drain region 150
Implementation Method 2
a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, wherein the first ion well and the second ion well have a junction at their interface
Data Source
AI summary
An HVMOS transistor structure includes: a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, wherein the first ion well and the second ion well have a junction at their interface; a gate overlying the first ion well and the second ion well; a drain region of the first conductivity type, in the first ion well, spaced apart from a first sidewall of the gate by an offset distance; and a source region of the first conductivity type in the second ion well. In addition, a method for fabricating the HVMOS transistor structure described above is also provided.