HVMOS Transistor Driving Current via Sacrificial Oxide Spacer
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Solution Overview
Problem
Conventional high voltage metal-oxide semiconductor (HVMOS) transistors suffer from poor etch selectivity during spacer formation, leading to surface damage, non-uniform driving current (Idsat), and performance degradation due to oxide depletion and poly damage.
Innovation Solution
The method involves forming a high voltage semiconductor device with a double diffused drain (DDD) structure, where a pair of spacers is created with a dielectric layer acting as an etch stop, and a second doped region is spaced apart from the gate electrode and isolation region, improving the etching process and reducing surface damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional spacer etching is used to form spacers, then the transistor structure can be formed, but surface damage region is created causing Idsat to drop
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary material between the substrate and the spacer formation process. This sacrificial oxide layer absorbs the etching damage that would otherwise directly affect the NDD/PDD region, preventing surface damage and maintaining stable driving current while still allowing spacer formation to proceed.
2Ease of manufacture
If spacer etching is performed, then spacers are formed for device structure, but oxide depletion and poly damage occur causing performance degradation
Solution Approach 1:
The sacrificial oxide layer serves as a protective intermediary that prevents direct etching contact with the gate oxide and polysilicon regions. This intermediary layer absorbs the harmful etching effects, preventing oxide depletion and poly damage while still allowing the spacer structure to be formed as required.
3Ease of manufacture
If etching process is used to form spacers, then spacers can be created, but poor etch selectivity causes non-uniform Idsat across wafer
Solution Approach 1:
The sacrificial oxide layer acts as a uniform intermediary across the entire wafer surface during the spacer etching process. This intermediary layer provides consistent etching conditions and damage absorption across all regions of the wafer, resulting in uniform Idsat values despite the inherent poor selectivity of the etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the driving current performance by increasing the mean Idsat by 15% and reducing non-uniformity by 87%, improving the reliability and stability of HVMOS transistors.
Implementation Method 1
at least one dielectric layer is formed over sidewalls of the gate electrode. A pair of spacers is formed on the dielectric layer
Implementation Method 2
A pair of spacers is formed on the dielectric layer. A preferred embodiment comprises a first doped region within the active region, wherein the first doped region comprises a portion underlying one of the spacers and a portion adjacent the one of the spacers
Data Source
AI summary
A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side boundary of the first doped region underlies part of the gate electrode. The second doped region is formed within the first doped region adjacent the gate electrode. A gate-side boundary of the second doped region is separated from a closest edge of a gate electrode spacer by a first distance. An isolation region-side boundary of the second doped region is separated from a closest edge of a nearest isolation region by a second distance.