HVMOS Transistor Trench Gate for Breakdown Voltage and RON Trade-off
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Solution Overview
Problem
High voltage metal-oxide-semiconductor (HVMOS) transistor devices face a trade-off between achieving high breakdown voltage and low resistance (RON), with existing lateral double-diffused MOS (LDMOS) transistors struggling to optimize both parameters simultaneously.
Innovation Solution
The HVMOS transistor device incorporates a substrate with a first insulating structure, a gate structure that penetrates into the base region, and conductivity type regions to enhance breakdown voltage and controllability, featuring a gate dielectric layer between the gate and conductivity type regions, allowing for increased breakdown voltage and improved gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then breakdown voltage can be increased through lateral-diffused drift region, but RON increases due to large area requirement
Solution Approach 1:
The gate structure extends vertically into the substrate through a trench, transitioning from a purely planar structure to a three-dimensional structure. This vertical extension allows the gate to control the channel more effectively without requiring a larger lateral area, thus reducing RON while maintaining high breakdown voltage through the drift region
Solution Approach 2:
The gate structure is nested within a trench that penetrates through the drift region into the substrate. The trench contains the gate dielectric layer and gate electrode, creating a compact structure where the gate is surrounded by the drift region, allowing better electrical control without increasing the device footprint
2Ease of operation
If gate structure penetrates into substrate, then controllability is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into distinct components: the trench structure, gate dielectric layer, and gate electrode. This segmentation allows each component to be optimized independently and formed through separate processing steps, making the complex structure manageable and manufacturable
Data Source
AI summary
A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.