HVNMOS Device With Segmented Buried Layers For Negative Voltage Isolation
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Solution Overview
Problem
Conventional high-voltage metal-oxide-semiconductor (HVMOS) devices experience increased leakage current and reduced breakdown voltage when subjected to negative source-to-substrate and drain-to-substrate voltages, limiting their performance in power IC and driver IC applications.
Innovation Solution
The semiconductor structure incorporates a p-type buried layer and n-type buried layer with high impurity concentrations, surrounded by high-voltage n-well and isolation regions, allowing for the formation of HVNMOS devices that can sustain both positive and negative source/drain-to-substrate voltages by isolating the devices within an n-type tub and utilizing epitaxial growth to enhance impurity diffusion and concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If n-type buried layer is used to support positive voltages, then device structure is simplified, but diode becomes forward biased under negative voltages causing increased leakage current
Solution Approach 1:
The semiconductor substrate is segmented into a first region with an n-type buried layer for positive voltage support and a second region with a p-type buried layer for negative voltage support. This segmentation allows each region to independently handle its voltage polarity without the other interfering, eliminating the forward biasing problem while maintaining structural simplicity in each segment.
Solution Approach 2:
The p-type buried layer in the second region acts as an intermediary structure that prevents the harmful forward biasing effect when negative voltages are applied. Instead of the n-type buried layer being directly forward-biased, the p-type layer serves as an intermediate region that manages the negative voltage stress differently, preventing excessive leakage current.
2Ease of manufacture
If single HVMOS device structure is used, then manufacturing process is simplified, but device cannot sustain both positive and negative source/drain-to-substrate voltages
Solution Approach 1:
The manufacturing process is segmented into separate processing streams for the first and second regions. Each region receives tailored implantation and processing steps optimized for its specific voltage requirements. The first region undergoes processing for positive voltage operation while the second region undergoes complementary processing for negative voltage operation, allowing both to be manufactured in the same substrate through systematic segmentation of the manufacturing flow.
Solution Approach 2:
The semiconductor substrate serves as a universal platform that can accommodate both types of HVMOS devices with complementary structures. The substrate and basic processing infrastructure are universal, but regional customization allows the same manufacturing system to produce devices with different optimized structures for positive and negative voltage operation within the same integrated circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage currents and maintains breakdown voltage integrity across various voltage conditions, enabling reliable operation of HVNMOS devices in applications with negative voltages.
Implementation Method 1
utilizing epitaxial growth to enhance impurity diffusion and concentration
Implementation Method 2
utilizing epitaxial growth to enhance impurity diffusion and concentration
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.