High-Voltage Stress Test Circuit With Low-Voltage Data Generation
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Solution Overview
Problem
Existing high voltage stress (HVS) test circuits for semiconductor devices require a large number of transistors using high supply voltage, leading to increased layout area and manufacturing costs due to the larger size of MOS transistors with high supply voltage compared to low supply voltage transistors.
Innovation Solution
The HVS test circuit design reduces the number of transistors using high supply voltage by employing an internal data generation unit that uses low supply voltage as a pull-up voltage and a level shifter that level-shifts the internal data to high supply voltage, allowing for reduced transistor count and layout area, while maintaining functionality in both normal and HVS test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high supply voltage transistors are used in HVS test circuit, then HVS test functionality is achieved, but layout area increases due to larger transistor size
Solution Approach 1:
The HVS test circuit is segmented into two distinct units: an internal data generation unit operating at low supply voltage and a level shifter operating at high supply voltage. This segmentation allows only the necessary components (level shifter and associated transistors) to use high supply voltage, minimizing the number of high voltage transistors while maintaining HVS test functionality.
Solution Approach 2:
Different parts of the circuit are assigned different supply voltages based on their functional requirements. The internal data generation unit uses low supply voltage for normal operation, while only the level shifter and specific transistors (131-136) use high supply voltage to achieve the HVS test effect, optimizing the layout area by limiting high voltage usage to essential components only.
2Reliability
If high supply voltage transistors are used in HVS test circuit, then HVS test mode is enabled, but manufacturing cost increases due to larger transistor size
Solution Approach 1:
The circuit is divided into low voltage and high voltage sections, with only essential components (level shifter transistors 131-136 and associated high voltage transistors) using high supply voltage. This segmentation reduces the total count of expensive high voltage transistors, thereby lowering manufacturing costs while preserving HVS test capability.
Solution Approach 2:
High supply voltage is applied locally only where necessary for HVS testing (in the level shifter and specific transistors), rather than throughout the entire circuit. This localized approach minimizes the number of high voltage transistors required, reducing manufacturing complexity and cost.
3Use of energy by moving object
If low supply voltage is used in internal data generation unit, then power consumption is reduced, but voltage level shifting is required for HVS test mode
Solution Approach 1:
The circuit is segmented into a low voltage internal data generation unit (reducing power consumption) and a high voltage level shifter (enabling HVS test mode). This segmentation allows the circuit to operate at low power during normal mode while providing the capability to switch to high voltage mode when needed, with the level shifter serving as the interface between the two voltage domains.
Solution Approach 2:
The level shifter acts as an intermediary between the low voltage internal data generation unit and the high voltage HVS test circuitry. It translates voltage levels from low to high, enabling the low power consumption benefits of low voltage operation while maintaining compatibility with high voltage components during HVS testing.
Data Source
AI summary
A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.