Hardware Acceleration Processor Nested Task Deadlock Resolution

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Solution Overview

Problem

Existing hardware-based task dependency management systems struggle with nested tasks, leading to memory full conditions and critical memory conflicts, which cause deadlocks and performance degradation, as they lack efficient mechanisms for handling these complexities.

Innovation Solution

The proposed solution involves a hardware acceleration processor with dedicated local memory and a communication mechanism that detects full memory conditions, stops new task reception, and reconstructs memory to manage nested task dependencies efficiently, using buffered and asynchronous communication to bypass thread interference and resolve deadlocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If hardware acceleration processor uses dedicated local memory to store task dependencies, then task dependency analysis speed is improved, but memory full conditions and critical memory conflicts occur leading to deadlocks

Engineering Contradiction:

Improvetask dependency analysis speedVSAvoidsystem deadlock prevention

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

A communication module acts as an intermediary between the hardware acceleration processor and the multi-core processor. When the dedicated local memory becomes full or experiences critical memory conflicts, the communication module detects these conditions and sends control signals to stop the hardware acceleration processor from accepting new tasks, preventing deadlocks while maintaining high processing speed for valid tasks

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If nested tasks are supported in hardware task management, then programmability and task parallelization are improved, but memory requirements and complexity increase

Engineering Contradiction:

Improvenested task supportVSAvoidmemory management complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The hardware acceleration processor implements nested task support by allowing child tasks to be created and managed within the context of parent tasks. The dedicated local memory stores dependency information for nested tasks using a structured format that tracks parent-child relationships and dependencies across multiple task levels, enabling complex nested task scenarios while maintaining efficient hardware-based management

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The communication module serves as an intermediary that manages the complexity of nested task memory requirements. It monitors memory usage patterns, detects when dedicated local memory becomes full, and coordinates with the multi-core processor to handle memory management, thereby reducing the complexity burden on the hardware acceleration processor itself

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If hardware acceleration processor continuously processes tasks, then productivity is improved, but memory conflicts and system deadlocks increase

Engineering Contradiction:

Improvetask processing throughputVSAvoidmemory conflict prevention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system implements feedback control through the communication module that continuously monitors the state of the dedicated local memory in the hardware acceleration processor. When memory full conditions or critical memory conflicts are detected, the communication module sends control signals to pause task acceptance, allowing the system to clear memory and resume processing, thereby preventing deadlocks while maintaining high productivity during normal operation

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables effective handling of nested task dependencies, prevents deadlocks, and improves performance by directly accessing system memory through DMA, reducing the burden on multi-core processors and enhancing memory management efficiency.

Implementation Method 1

allocating data buffers in system memory for each thread running in each multi-core processing element; sending system memory address and length of buffers used in a communication to the hardware acceleration processor, using buffered and asynchronous communication; the hardware acceleration processor directly accessing the buffers bypassing the threads running in the parallel processing elements

Methodology Applied

Scientific EffectDirect Memory Access (DMA):

Data Source

PatentUS11436048B2Method of managing task dependencies at runtime in a parallel computing system of a hardware processing system and a hardware acceleration processor

Publication Date: 2022.09.06 BARCELONA SUPERCOMPUTING CENT CENT NAT DE SUPERCOMPUTACION

AI summary

Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.