Hardware Accelerated Communication Frame for Power Systems

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Solution Overview

Problem

Frame-based communication systems in electrical power delivery systems face delays due to processor-dependent data gathering and frame population, which reduces the utility of data for receiving devices and increases latency in communication and protection operations.

Innovation Solution

The implementation of hardware-accelerated communication frames using integrated circuits like FPGAs, which include pre-payload circuitry for preset metadata and payload generation circuitry to generate data quickly, reducing the reliance on processors and accelerating the transmission of communication frames.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If processor-dependent data gathering and frame population is used, then communication frame transmission is achieved, but latency increases and transmission speed decreases

Engineering Contradiction:
Improvetransmission speedVSAvoidlatency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent replaces the software-based processor-dependent frame population mechanism with a hardware-based field-populated frame structure. Specific fields (destination address, source address, length/type, VLAN, ethertype) are pre-populated in hardware circuits rather than being generated by processor execution, thereby eliminating software processing delays and significantly reducing latency while increasing transmission speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Loss of time

If hardware-accelerated communication frames with pre-populated fields are used, then transmission latency is reduced, but device complexity increases

Engineering Contradiction:
ImprovelatencyVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the communication frame into distinct fields, each with a specific function (destination address, source address, length/type, VLAN, ethertype, payload). By pre-populating specific segments in hardware while allowing others to be dynamically generated, the system achieves latency reduction without requiring complete hardware reconfiguration, thus managing device complexity through functional segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-populating certain frame fields (destination address, source address, length/type, VLAN, ethertype) in hardware circuits before the actual communication event occurs. This pre-configured data is immediately available when needed, eliminating real-time processing delays and reducing latency without requiring complex runtime decision-making.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11128481B2Hardware accelerated communication frame
Publication Date: 2021.09.21 SCHWEITZER ENGINEERING LABORATORIES INC
  • US11128481B2 patent drawing
  • US11128481B2 patent drawing
  • US11128481B2 patent drawing

AI summary

Disclosed herein are systems for hardware accelerated communications between devices for the protection of electric power delivery systems. For example, a merging unit may include input circuitry that receives a monitoring signal indicating an electrical characteristic of a power line. The merging unit may include pre-payload circuitry that generates at least portions of preset metadata of a communication frame. The merging unit may include payload generation circuitry that generates payload data of the communication frame based at least in part on the electrical characteristic. The merging unit may include a communication interface that sends the communication frame to a receiving device.