Hardware Buffer Management for Parallel DMA Task Processing
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Solution Overview
Problem
Current buffer management algorithms for multi-channel Direct Memory Access (DMA) in intelligent hardware are processor-intensive, leading to high processor utilization and slow task processing speeds due to serial and synchronous execution modes, which bottleneck data transmission performance.
Innovation Solution
Implementing a task processing method that uses parallel execution by a hardware device with pipeline parallel processing, creating storage queues for different processing stages, and performing load balancing on page index queues to reduce processor utilization and improve buffer management algorithm performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If buffer management algorithm is executed by processor software in serial mode, then task processing can be completed, but processor utilization rate increases and task processing speed decreases
Solution Approach 1:
The patent replaces the software-based buffer management algorithm with a hardware-based implementation. The hardware device executes the buffer management algorithm through parallel processing mechanisms, substituting the mechanical/software execution model with a hardware-based parallel execution model. This resolves the contradiction by achieving both high processor utilization (software remains free for application programs) and high task processing speed (hardware parallel processing).
Solution Approach 2:
The patent segments the buffer management processing into multiple parallel channels handled by different hardware processing units. Each channel can process buffer management requests independently and simultaneously, transforming the serial processing model into a parallel architecture. This segmentation enables simultaneous execution of multiple buffer management operations, increasing throughput while reducing processor software involvement.
2Productivity
If software executes buffer management algorithm synchronously, then correctness is ensured, but data transmission performance bottlenecks occur when there are too many DMA channels
Solution Approach 1:
The patent replaces the synchronous software execution model with asynchronous hardware-based parallel processing. The hardware device processes multiple DMA channel buffer management requests concurrently without requiring sequential software intervention. This substitution eliminates the performance bottleneck caused by synchronous software execution while maintaining system correctness through hardware-level protocol enforcement.
Solution Approach 2:
The patent introduces a hardware buffer management device as an intermediary between the DMA channels and the processor software. This intermediary handles buffer allocation, status tracking, and coordination for multiple DMA channels independently of the main processor, distributing the management complexity away from the central software system and enabling scalable performance.
3Reliability
If high processor utilization is used for buffer management, then buffer allocation can be managed, but application program execution is adversely affected
Solution Approach 1:
The patent replaces processor software execution of the buffer management algorithm with dedicated hardware circuitry. The hardware device autonomously manages buffer allocation, status tracking, and DMA channel coordination without requiring processor software intervention. This substitution ensures reliable buffer management through dedicated hardware logic while freeing the processor to focus entirely on application program execution, eliminating the resource contention between buffer management and application processing.
Data Source
AI summary
A task processing method includes: acquiring a plurality of to-be-processed tasks; the plurality of to-be-processed tasks corresponding to a plurality of buffer management request sets; creating different storage queues for storing information of different processing stages for each of the plurality of buffer management request sets to obtain a plurality of storage queue sets corresponding to the plurality of buffer management request sets; processing the plurality of to-be-processed tasks in parallel by hardware, processing different buffer management requests in the buffer management request sets in a pipeline parallel mode, and storing information of corresponding processing stages by utilizing different storage queues in the plurality of storage queue sets. By means of the aforesaid method, tasks are collaboratively processed by software and hardware, so that the performance of a buffer management algorithm is improved, and the speed of task processing is further increased.