Hardware Software Partitioning for Programmable Logic Devices
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Solution Overview
Problem
Designing electronic circuits specified in high-level programming languages poses challenges in balancing hardware and software implementation, particularly in programmable logic devices (PLDs), where resource constraints and performance optimization are difficult to manage, leading to costly and complex analysis and implementation processes.
Innovation Solution
A method and apparatus that compiles high-level programming language programs into target language programs with functional elements, profiles their execution, and selectively implements subsets in programmable logic devices based on resource availability, generating a bitstream for hardware implementation and processing the remaining elements in software, allowing for dynamic or static reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a high-level programming language program is implemented entirely in software on a processor, then ease of modification and reconfigurability are improved, but performance and execution speed deteriorate
Solution Approach 1:
The system dynamically determines at runtime which functional elements should be implemented in hardware versus software. The processor executes the target language program, profiles execution counts, and selectively configures the PLD to implement frequently-executed functions in hardware, while keeping less frequent functions in software. This dynamic adaptation resolves the contradiction between reconfigurability and execution speed.
Solution Approach 2:
The program is segmented into functional elements that are independently analyzed and selectively implemented. The system divides the high-level program into discrete functional elements, evaluates their execution characteristics through profiling, and partitions them between hardware (PLD) and software (processor) implementations based on performance requirements and resource availability.
2Speed
If frequently executed functional elements are implemented in hardware, then execution speed is improved, but device complexity and resource usage increase
Solution Approach 1:
The system uses execution profiling feedback to make informed decisions about hardware implementation. The processor executes the target language program and collects profile data on execution counts of functional elements. This feedback information is used to selectively implement only those functional elements with high execution counts in hardware, optimizing the balance between performance improvement and hardware resource consumption.
3Manufacturing precision
If manual analysis and selection of hardware/software partitioning is performed, then design precision can be improved, but productivity and design time deteriorate
Solution Approach 1:
The system performs automated hardware/software partitioning without requiring manual designer intervention. The compiler automatically compiles the high-level program to target language, the processor automatically profiles execution characteristics, and the system automatically selects which functional elements to implement in hardware based on execution counts and resource availability. This self-service approach maintains design precision while dramatically improving productivity.
Solution Approach 2:
The system performs preliminary compilation and profiling actions to gather necessary information before making partitioning decisions. The high-level program is first compiled to target language with functional element identification, then executed to collect profile data on execution counts. This preliminary analysis enables subsequent automated, precise partitioning decisions without time-consuming manual review.
4Speed
If the design is separated into hardware and software components, then performance optimization is improved, but device complexity and implementation difficulty increase
Solution Approach 1:
The system uses a universal target language that can represent both hardware and software implementations of functional elements. The same target language program serves as the basis for both the software execution on the processor and the hardware implementation in the PLD. This multi-functionality approach simplifies the implementation process by using a single language and unified workflow for both hardware and software components.
Data Source
AI summary
Various approaches are described for implementing a high-level programming language program in hardware and software components. In one approach, a method comprises compiling the high-level programming language program into a target language program that includes a plurality of functional elements. Execution of the target language program is profiled to obtain execution counts of the functional elements. A subset of the functional elements are selected for implementation in programmable resources of a programmable device based on the profile data and availability of programmable resources. A bitstream is generated to implement a first sub-circuit that performs functions of the subset of functional elements, and the subset of functional elements is removed from the target language program. The programmable device is configured with the bitstream. The target language program is provided for execution by a processor.