Hardware Virtual Switch Interconnect Assignment for VMs

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Solution Overview

Problem

Software-based open virtual switching (OVS) solutions in data centers consume significant CPU resources, leading to reduced throughput and increased latency, especially with the increasing demand for data traffic and 5G wireless technology, which requires more efficient virtual switching to handle multiple virtual machines and network functions.

Innovation Solution

A processor and hardware acceleration system that extends the processor coherency domain to include multi-processor cache, system memory, and accelerator cache, using a multi-chip package with device interface units and acceleration function units to abstract physical interconnects into virtual channels, allowing for dynamic assignment of interconnects based on workload characteristics, thereby optimizing hardware acceleration for virtual machines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based virtual switching is used to handle multiple VMs and network functions, then versatility and adaptability are improved, but CPU resource consumption increases and throughput decreases

Engineering Contradiction:
Improvevirtual switching capabilityVSAvoiddata plane throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a hardware-based virtual switching intermediary that mediates between VMs and the network. This hardware switch operates independently from the server CPU, using dedicated forwarding planes and buffer memory to handle packet switching operations. The hardware switch receives packets from VMs via paravirtualized drivers, performs forwarding decisions using flow tables, and transmits packets to the network without involving the server CPU in the data path, thus resolving the contradiction between software-based versatility and hardware-based throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If software-based virtual switching is used to provide comprehensive networking features, then ease of operation and functionality are improved, but latency increases due to CPU processing overhead

Engineering Contradiction:
Improvevirtual switching functionalityVSAvoidpacket forwarding latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces the mechanical CPU processing system with a dedicated hardware switching system. Instead of using general-purpose CPU cycles to make forwarding decisions, the hardware switch uses specialized forwarding engines that consult flow tables stored in dedicated memory. This substitution eliminates CPU context switching, cache misses, and instruction pipeline stalls that contribute to latency, while maintaining full virtual switching functionality through hardware-based flow table management and packet processing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If hardware-based virtual switching is used to improve throughput and reduce latency, then productivity is improved, but device complexity and infrastructure cost increase

Engineering Contradiction:
Improvedata plane throughputVSAvoidhardware infrastructure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the networking function into distinct components: a hardware virtual switch with dedicated forwarding planes, buffer memory, and flow table storage; paravirtualized drivers in the VM; and a control plane for flow table management. This segmentation allows the hardware switch to focus solely on high-speed packet forwarding while other components handle configuration and control functions. The modular architecture reduces overall system complexity by separating concerns and allowing each component to be optimized independently.

Inventive Principle:
Principle #1Segmentation

4Adaptability or versatility

If server CPU resources are allocated to virtual switching operations, then virtual switching capability is improved, but application performance deteriorates due to reduced available CPU resources

Engineering Contradiction:
Improvevirtual switching capabilityVSAvoidCPU resource availability
Core Design Contradiction:
Adaptability or versatilityVSPower

Solution Approach 1:

The patent extracts the packet forwarding function from the server CPU and relocates it to a dedicated hardware virtual switch. The hardware switch independently handles all data plane packet processing, including receiving packets from VMs via paravirtualized drivers, making forwarding decisions using flow tables, and transmitting packets to the network. This extraction completely removes the CPU overhead associated with virtual switching operations, making all CPU resources available for application workloads while maintaining full virtual switching capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11249779B2Accelerator interconnect assignments for virtual environments
Publication Date: 2022.02.15 INTEL CORP
  • US11249779B2 patent drawing
  • US11249779B2 patent drawing
  • US11249779B2 patent drawing

AI summary

A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.