Hybrid Access Transistor Stacking for Stable Hysteretic Memory
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Solution Overview
Problem
Current memory technologies face challenges in achieving high-density and low-power consumption while maintaining adequate non-volatility and scalability, particularly with hysteretic memory cells that struggle to prevent polarization state disturbances due to non-square hysteresis loops.
Innovation Solution
The implementation of hybrid manufacturing of access transistors for memory, which includes combining transistors of different architectures and hysteretic capacitors in a vertically stacked architecture, allowing for increased active memory layers with fewer masks and lower costs, and employing access transistors to control hysteretic memory cells, thereby enhancing density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If hysteretic memory cells are used to achieve high-density and low-power consumption, then memory density and power efficiency are improved, but polarization state disturbances occur due to non-square hysteresis loops
Solution Approach 1:
An access transistor is introduced as an intermediary component between the control circuit and the hysteretic memory cell. The transistor's gate controls the flow of charge to and from the hysteretic element, enabling precise control of polarization states. This mediator prevents direct uncontrolled charging/discharging that causes polarization disturbances, while still allowing the hysteretic cell to maintain its high-density and low-power advantages.
2Quantity of substance
If vertically stacked architecture is implemented to increase active memory layers, then memory density is improved, but manufacturing complexity increases
Solution Approach 1:
The memory architecture transitions from a planar two-dimensional layout to a vertical three-dimensional stacked structure. Multiple memory layers are stacked above each other, with through-silicon vias (TSVs) and interconnect structures enabling vertical connectivity. This dimensional change allows significantly increased memory capacity within the same footprint area, achieving higher density without proportionally increasing manufacturing complexity by using established vertical stacking processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases memory density and reduces costs, enabling high-density embedded memory compatible with advanced CMOS processes while improving the stability of hysteretic memory cells by using access transistors to manage voltage effects.
Implementation Method 1
hysteretic memory cells that struggle to prevent polarization state disturbances due to non-square hysteresis loops
Data Source
AI summary
Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.