Hybrid A-D Converter Using Flash and SAR Bit Segmentation
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Solution Overview
Problem
Existing A-D converters face challenges in achieving high resolution and short conversion time while maintaining precision, as both single-bit and multi-bit converters experience increased power consumption and decreased precision due to narrowed quantization ranges and signal noise, especially when amplifying input signals.
Innovation Solution
The proposed A-D converter employs a two-step conversion process using a plurality of comparators to compare analog input signals with threshold values, narrowing down data values in the upper field through flash conversion and determining lower field bits through successive approximation, while ignoring the upper field to reduce power consumption and enhance precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-bit A-D converter is used to achieve high resolution, then conversion time is reduced, but circuit size becomes large
Solution Approach 1:
The digital output signal is divided into upper field bits and lower field bits. The upper field determination section processes the upper field bits using flash conversion with multiple comparators, while the lower field determination section processes the lower field bits using successive approximation. This segmentation allows the circuit to achieve high resolution without requiring a fully parallel multi-bit architecture for all bits, thereby reducing overall circuit size while maintaining fast conversion time.
2Area of stationary object
If a single-bit A-D converter is used to reduce circuit size, then conversion time becomes long
Solution Approach 1:
The conversion process is segmented into two phases: upper determination phase using flash conversion (parallel processing with multiple comparators) for upper field bits, and lower determination phase using successive approximation for lower field bits. This hybrid approach combines the speed of parallel conversion for significant bits with the circuit efficiency of sequential conversion, achieving fast overall conversion time with reduced circuit complexity compared to full parallel conversion.
3Measurement precision
If high resolution is realized by narrowing quantization range, then precision decreases due to signal noise
Solution Approach 1:
The invention extracts and processes the upper field bits (more significant bits) separately from the lower field bits (less significant bits). By determining the upper field bits first through flash conversion and then using those results to guide the successive approximation for lower field bits, the system effectively separates the processing of significant precision-determining bits from less significant bits, maintaining precision while achieving high resolution.
4Reliability
If the input signal is amplified by an operational amplifier to solve precision issues, then power consumption increases
Solution Approach 1:
The threshold values supplied to the comparators are dynamically adjusted based on the conversion phase and previously determined bit values. During the upper determination phase, fixed threshold values are used for flash conversion. During the lower determination phase, the threshold control section dynamically determines threshold data values based on predetermined values of higher bits, allowing the comparators to operate with optimized thresholds that reduce the need for signal amplification and associated power consumption.
Data Source
AI summary
An A-D converter includes a plurality of comparators, each of which compares an analog input signal to analog threshold values; an upper field determination section which, during an upper determination phase, supplies in parallel to each of the plurality of comparators the plurality of analog threshold values expressing boundaries of ranges corresponding to each data value acquired from the upper field of a number of bits previously designated in the digital output signal, detects whether the analog input signal is associated with one of the ranges based on comparison results by the plurality of comparators, and narrows data values of the upper field to data values corresponding to a range between the largest analog threshold value less than or equal to the analog input signal and the smallest analog threshold value greater than or equal to the analog input signal; and a lower field determination section which, during the lower determination phase, determines values of conversion target bits based on a plurality of comparison results of the plurality of comparators.