Hybrid SAR-Ramp ADC Code Correction for Imaging Sensors
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Solution Overview
Problem
Conventional hybrid ramp-SAR ADC architectures in imaging devices experience non-ideal behavior due to ADC non-linearity and code mismatch at the transition between SAR and ramp conversion, leading to degraded performance characterized by higher differential nonlinearity and missing/repeated codes, which result in artifacts like fixed pattern noise.
Innovation Solution
The implementation of hybrid SAR-ramp ADC circuitry with error correction techniques, including the injection of a voltage offset and extension of the voltage range of the ramp ADC circuitry, to align the ramp range with the SAR least significant bit, thereby reducing non-idealities and improving conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hybrid ramp-SAR ADC architecture is used to improve conversion speed and resolution, then ADC performance is improved, but non-ideal behavior occurs due to non-linearity and code mismatch at transition
Solution Approach 1:
The patent applies preliminary action by performing calibration of the ramp ADC circuitry before actual image signal conversion. During calibration, test signals are converted and used to determine correction values that compensate for non-linearity and code mismatch. These correction values are stored and applied during subsequent normal operation, preventing the non-ideal behavior from occurring during actual imaging.
Solution Approach 2:
The patent implements feedback by using the output codes from the ramp ADC during calibration to calculate correction values. The calibration process measures the actual conversion characteristics and generates feedback in the form of correction data that is used to adjust the ramp ADC operation, thereby compensating for non-linearity and code mismatch issues.
2Measurement precision
If ramp ADC circuitry is added to improve resolution, then ADC performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the ramp ADC and SAR ADC into a hybrid architecture where both converters work together. The SAR ADC handles the most significant bits quickly, while the ramp ADC provides high-resolution least significant bits. This combination allows the system to achieve high overall resolution while maintaining reasonable conversion speed, as each converter is optimized for its specific function rather than requiring one converter to handle all requirements.
Solution Approach 2:
The patent segments the ADC conversion process into two distinct phases: SAR conversion for the most significant bits and ramp conversion for the least significant bits. This segmentation allows each converter to be optimized independently for its specific task, with the SAR ADC providing fast coarse conversion and the ramp ADC providing precise fine conversion, thereby managing complexity through functional division.
3Measurement precision
If calibration and correction circuitry is added to reduce non-linearity, then measurement precision is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies self-service by designing a calibration system that automatically characterizes and corrects its own non-linearities without requiring external manual calibration. The calibration circuitry generates test signals, measures the actual conversion characteristics, calculates correction values, and stores them for automatic application during normal operation. This self-calibrating approach simplifies manufacturing by eliminating the need for complex manual calibration procedures while maintaining high precision.
Data Source
AI summary
Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.