Hybrid Oversampled ADC with Delta-Sigma and Cyclic Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Hybrid analog-to-digital converters face challenges in achieving high resolution with reduced conversion time and minimizing differential non-linearity due to capacitor mismatch, while maintaining reasonable noise performance and circuit area.
Innovation Solution
A hybrid ADC that combines delta-sigma and cyclic conversion techniques, utilizing a multi-bit quantizer and calibration circuit to reduce conversion time and DNL, with a switched capacitor amplifier and capacitive digital-to-analog converter for efficient bit generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delta-sigma conversion is used to achieve high resolution, then measurement precision is improved, but conversion time increases
Solution Approach 1:
The conversion process is segmented into two distinct phases: delta-sigma conversion for the first N bits and cyclic conversion for the remaining bits. This segmentation allows each method to operate in its optimal regime, with delta-sigma providing high-resolution initial conversion and cyclic conversion completing the process more quickly, thereby reducing overall conversion time while maintaining high resolution
Solution Approach 2:
The ADC dynamically switches between two conversion modes based on the conversion stage. The control logic automatically transitions from delta-sigma mode to cyclic mode after N bits are converted, optimizing the conversion process by using the appropriate method for each stage rather than relying on a single static conversion approach
2Manufacturing precision
If capacitor size is increased to reduce differential non-linearity, then manufacturing precision is improved, but device area increases
Solution Approach 1:
The patent uses smaller capacitors that would normally be insufficient for high-precision conversion, but compensates through the hybrid conversion methodology. The multi-bit quantizer and calibration circuit effectively compensate for the reduced capacitor size, achieving accurate conversion without requiring large capacitors that would increase circuit area
Solution Approach 2:
The system changes the conversion parameters by switching between delta-sigma and cyclic modes, and uses calibration to adjust for errors introduced by smaller capacitors. This allows the use of reduced capacitor sizes while maintaining conversion accuracy through digital compensation rather than relying solely on large physical capacitors
3Productivity
If multi-bit quantization is used to reduce conversion time, then productivity is improved, but noise performance deteriorates
Solution Approach 1:
The quantization process is segmented where the multi-bit quantizer operates during cyclic conversion to provide fast conversion, while the delta-sigma portion handles the initial high-precision quantization. This segmentation allows the system to leverage the speed of multi-bit quantization without fully exposing the noise drawbacks, as the delta-sigma stage provides a cleaner initial conversion
Solution Approach 2:
The calibration circuit provides feedback to compensate for noise and errors introduced by multi-bit quantization. By measuring and correcting for quantization noise and DNL errors, the system can use aggressive multi-bit quantization for speed while maintaining noise performance through digital feedback compensation
4Measurement precision
If calibration circuit is added to reduce DNL, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces physical capacitor sizing adjustments with a digital calibration circuit that compensates for DNL errors through digital processing. Instead of using larger capacitors to inherently reduce DNL, the system uses software-based calibration algorithms to correct for capacitor mismatches, thereby reducing DNL without increasing analog circuit complexity
Data Source
AI summary
A circuit includes a switched capacitor amplifier circuit, a multi-bit quantizer circuit, an accumulator circuit, a cyclic result register, and a result combination circuit. The switched capacitor amplifier circuit has an output. The multi-bit quantizer circuit has an input coupled to the output of the switched capacitor amplifier circuit, and an output. The accumulator circuit has an input coupled to the output of the multi-bit quantizer circuit, and an output. The cyclic result register has an input couped to the output of the multi-bit quantizer, and an output. The result combination circuit has a first input coupled to the output of the accumulator circuit, and a second input coupled to the output of the cyclic result register.