Hybrid ADC Mode Switching for High Dynamic Range Imaging
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Solution Overview
Problem
Existing image sensor technologies face challenges in increasing high dynamic range without compromising frame rate or increasing power consumption and silicon area, particularly in ramp analog-to-digital converters.
Innovation Solution
The implementation of hybrid analog-to-digital converters (ADCs) that operate in dual modes, using successive approximation register (SAR) ADC mode for most significant bits and ramp ADC mode for least significant bits, sharing components like comparators to reduce component count and power consumption, while allowing for increased resolution without significant increases in counter time or power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counter resolution is increased to increase high dynamic range, then measurement precision is improved, but conversion time increases and frame rate decreases
Solution Approach 1:
The patent divides the ADC conversion process into two segments: a first conversion mode (e.g., ramp ADC) that provides coarse resolution, and a second conversion mode (e.g., SAR ADC) that provides fine resolution. This segmentation allows the system to achieve high overall resolution without requiring the counter to count through all possible values, thereby maintaining high frame rates while improving measurement precision.
2Measurement precision
If counter resolution is increased to increase high dynamic range, then measurement precision is improved, but conversion time increases
Solution Approach 1:
The conversion process is segmented into two stages: a first conversion mode that quickly establishes a coarse digital value, and a second conversion mode that refines this value to achieve high resolution. This segmentation significantly reduces the total conversion time compared to a single high-resolution conversion, as the second mode can operate from a pre-established baseline rather than starting from zero.
3Measurement precision
If noise on ramp generator is reduced to increase high dynamic range, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent segments the conversion process so that the power-intensive high-resolution conversion (second mode) is only activated when needed to refine the digital output, rather than running continuously at full power. The first conversion mode operates at lower power to establish the coarse value, thereby reducing overall power consumption while maintaining the ability to achieve high dynamic range when required.
4Measurement precision
If noise on ramp generator is reduced to increase high dynamic range, then measurement precision is improved, but silicon area increases
Solution Approach 1:
The patent designs the ADC system with multi-functional components that can operate in different conversion modes. The same hardware infrastructure supports both the first conversion mode (e.g., ramp ADC) and the second conversion mode (e.g., SAR ADC), allowing the system to achieve high dynamic range without requiring separate dedicated circuits for each function, thereby minimizing silicon area usage.
Data Source
AI summary
A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.