Hybrid ADC Architecture Using Time-Domain Residue Quantization
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Solution Overview
Problem
High-resolution analog-to-digital converters face challenges in achieving high-speed and low-power performance due to increased power consumption and noise requirements, particularly in deep submicron CMOS technology, where voltage domain amplifiers are power-hungry and sensitive to process-voltage-temperature variations, limiting their suitability for fine quantization.
Innovation Solution
A hybrid pipelined ADC architecture that includes a successive-approximation-register (SAR) ADC stage for voltage domain quantization, a ring time-to-digital converter (TDC) stage for time domain quantization, and an interpolation TDC stage, with a discharging-based voltage-to-time converter (VTC) inter-stage to convert voltage residues to time domain, reducing power consumption and noise requirements while maintaining high resolution and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage domain amplifiers are used in deep submicron CMOS technology to achieve high resolution, then measurement precision is improved, but power consumption increases and the system becomes sensitive to PVT variations
Solution Approach 1:
The patent changes the operating domain from voltage to time, using time domain quantization instead of voltage domain amplification. This parameter change allows achieving high resolution without the power consumption and PVT sensitivity issues inherent in voltage domain amplifiers in deep submicron CMOS technology.
Solution Approach 2:
The patent substitutes voltage domain amplification with time domain processing. Instead of using power-hungry voltage amplifiers to achieve gain and resolution, the system uses time-to-digital conversion where the residue voltage is converted to a time interval, which is then quantized in the time domain, eliminating the need for high-gain voltage amplifiers.
2Measurement precision
If voltage domain amplifiers are used to provide gain for high resolution quantization, then measurement precision is improved, but the system becomes sensitive to process-voltage-temperature variations
Solution Approach 1:
The patent changes the domain of quantization from voltage to time. By converting the voltage residue to a time interval and performing quantization in the time domain, the system achieves high resolution without relying on high-gain voltage amplifiers that are sensitive to PVT variations, thereby improving reliability.
Solution Approach 2:
The patent replaces the voltage domain amplification and quantization mechanism with a time domain mechanism. The voltage-to-time converter transforms the residue voltage into a time interval, which is then quantized by a time-to-digital converter. This substitution eliminates the PVT sensitivity inherent in voltage domain amplifiers while maintaining high resolution.
3Measurement precision
If pipeline architecture with inter-stage amplifiers is used to achieve medium-to-high resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent changes the quantization domain from voltage to time in the pipeline architecture. By using a voltage-to-time converter followed by a time domain quantizer, the system achieves medium-to-high resolution without requiring power-hungry inter-stage voltage amplifiers, thus reducing overall power consumption while maintaining resolution performance.
Solution Approach 2:
The patent substitutes the conventional voltage domain pipeline architecture with a hybrid architecture that uses time domain quantization. The inter-stage converter transforms voltage residues to time intervals, and the time domain quantizer processes these intervals without requiring high-gain voltage amplifiers, thereby reducing power consumption while achieving the desired resolution.
4Productivity
If flash ADC topology is used to achieve high conversion speed, then productivity is improved, but device complexity increases exponentially for medium-to-high resolution
Solution Approach 1:
The patent segments the conversion process into two stages: a coarse quantization stage that handles the majority of the conversion speed requirement and a fine quantization stage in the time domain that adds resolution. This segmentation allows achieving high conversion speed without the exponential hardware complexity increase associated with high-resolution flash ADCs.
Solution Approach 2:
The patent changes the domain of the fine quantization stage from voltage to time. By converting the residue voltage to a time interval and performing fine quantization in the time domain, the system achieves high resolution with moderate hardware complexity while maintaining high conversion speed, avoiding the exponential complexity growth of conventional high-resolution flash ADCs.
Data Source
AI summary
An analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.