Hybrid Pipelined ADC Using Inter-Stage Voltage-to-Time Conversion
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Solution Overview
Problem
High-resolution analog-to-digital converters face challenges in achieving high-speed and low-power performance due to increased power consumption and noise requirements, particularly in deep submicron CMOS technology, where voltage domain amplifiers are power-hungry and sensitive to process-voltage-temperature variations.
Innovation Solution
A hybrid pipelined ADC architecture that employs multi-domain signal processing, including voltage, current, time, frequency, and charge domains, with a first converter stage for voltage domain quantization and a second stage for time domain quantization, using inter-stage converters like voltage-to-time converters to match residue signal ranges, enabling simultaneous operation and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pipeline ADC architecture is used to achieve medium-to-high resolution, then resolution is improved, but power consumption increases due to power-hungry inter-stage amplifiers
Solution Approach 1:
The ADC is divided into multiple pipeline stages, each handling a portion of the conversion process. This segmentation allows the system to achieve high resolution through cumulative quantization across stages while reducing the burden on individual amplifiers, thereby lowering overall power consumption compared to a single-stage high-resolution converter.
Solution Approach 2:
The patent introduces time-domain processing as an additional dimension alongside traditional voltage-domain processing. By converting voltage residues to time intervals and processing them in the time domain, the system achieves high resolution without requiring high-gain voltage amplifiers, thus reducing power consumption in inter-stage amplification.
2Speed
If flash ADC architecture is used to achieve high conversion rate, then speed is improved, but hardware complexity and power consumption increase exponentially
Solution Approach 1:
The flash ADC's single-stage high-speed conversion is segmented into multiple pipeline stages, each performing coarse quantization. This segmentation maintains high conversion rate by allowing parallel processing across stages while dramatically reducing the number of comparators and logic required in each stage compared to a full flash architecture.
Solution Approach 2:
Each pipeline stage performs partial quantization (coarse conversion) rather than complete high-resolution conversion. This partial action approach allows the system to achieve overall high resolution through multiple stages while keeping each stage's hardware complexity manageable, avoiding the exponential complexity of a single-stage flash ADC.
3Use of energy by moving object
If SAR ADC architecture is used to achieve power efficiency, then power consumption is reduced, but conversion speed degrades at high resolution
Solution Approach 1:
The patent merges the advantages of SAR ADC (power efficiency) with pipeline ADC (high conversion rate) by using SAR ADCs as individual pipeline stages. Each stage operates as a power-efficient SAR converter, and the pipelined architecture enables simultaneous operation of multiple stages, achieving both low power consumption and high conversion rate.
Solution Approach 2:
Each pipeline stage performs preliminary (coarse) quantization before passing the residue to the next stage. This preliminary action approach allows early stages to quickly establish coarse digital values, enabling the overall system to achieve high conversion rate while maintaining the power efficiency of SAR ADC operation at each stage.
4Power
If voltage domain amplifiers are used in deep submicron CMOS, then voltage gain is achieved, but power consumption increases and performance becomes sensitive to PVT variations
Solution Approach 1:
The patent introduces time-to-voltage converters and voltage-to-time converters as intermediary devices between voltage domain stages. These converters translate voltage signals to time domain representations, eliminating the need for high-gain voltage amplifiers in deep submicron CMOS. The time domain processing maintains signal integrity without requiring power-hungry amplification, reducing both power consumption and PVT sensitivity.
Data Source
AI summary
An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.