Hybrid Address Translation via SLB Type Field
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Solution Overview
Problem
Current address translation mechanisms in computer systems are inefficient, as they rely on complex procedures that can hinder processor performance, especially when dealing with virtual memory translations that are not cached in ERAT, SLB, or TLB, leading to potential page table searches that increase clock cycle time.
Innovation Solution
Implementing a hybrid address translation system that uses both hashed page tables (HPT) and radix trees, with SLB entries indicating the type of search required, allowing for efficient translation of addresses based on the type of request and OS, optimizing performance for sparse and localized memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a page table search is performed when the effective address is not in ERAT, SLB, or TLB caches, then the correct translation can be determined, but the clock cycle time increases and processor performance decreases
Solution Approach 1:
The system performs preliminary actions by checking multiple cache structures (ERAT, SLB, TLB) before performing a full page table search. The SLB is pre-configured with type fields that indicate whether HPT or radix tree search should be used, so when an address is found in SLB, the appropriate translation structure is already identified and ready for quick access.
Solution Approach 2:
The address translation process is segmented into multiple stages: first check ERAT cache, then SLB, then TLB, and only if all fail then perform page table search. The SLB is further segmented into different types (HPT type and radix tree type) to handle different translation scenarios efficiently. This segmentation allows the system to handle common cases quickly while reserving full search capability for rare cases.
2Device complexity
If a single address translation method is used for all applications, then the system is simpler to implement, but performance is reduced for applications with different memory access patterns
Solution Approach 1:
The system dynamically selects the appropriate address translation method (HPT or radix tree) based on the type field in the SLB entry corresponding to the effective address. This dynamic selection allows the system to adapt to different application requirements and memory access patterns without requiring manual configuration or complex decision logic in the translation path itself.
Solution Approach 2:
The SLB structure serves multiple functions: it stores translation information, indicates the type of search required (HPT or radix tree), and provides the basis for dynamic method selection. This multi-functionality allows a single data structure to support both simplicity (by providing ready-made type information) and performance (by enabling optimal method selection for each application).
Data Source
AI summary
Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.