Hybrid Address Translation Cache Using DRAM for Lower SSD Costs

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Solution Overview

Problem

The existing address translation cache (ATC) solutions in SSDs are expensive, consume high power, and inefficient due to the need for large memory buffers and high-performance look-up operations, leading to increased area, cost, and power consumption.

Innovation Solution

Splitting the ATC into two portions, with one portion in the controller's SRAM and the other in a host memory buffer (HMB) or DRAM, allowing untranslated addresses to be searched in the first portion and translated addresses retrieved from the second portion, while invalidating untranslated addresses in the first portion without affecting the second.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a real cache for ATC is implemented as defined in PCIe standard, then address translation functionality is supported, but area, cost and power consumption significantly increase

Engineering Contradiction:

Improveaddress translation functionalityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The ATC is segmented into two separate portions: a first portion stored in controller memory (SRAM/DRAM) and a second portion stored in host memory buffer (HMB). This segmentation allows the device to maintain address translation functionality while significantly reducing the area occupied in the controller, as the larger portion is offloaded to host memory.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The host memory buffer (HMB) acts as an intermediary storage location for the second portion of the ATC. Instead of requiring all ATC data to reside in controller memory, the HMB serves as a mediator that provides additional storage capacity while maintaining accessibility for address translation operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a real cache for ATC is implemented as defined in PCIe standard, then address translation functionality is supported, but power consumption significantly increases

Engineering Contradiction:

Improveaddress translation functionalityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

By segmenting the ATC into two portions located in different memory spaces, the invention reduces power consumption. The first portion in controller memory handles frequently accessed translations, while the second portion in HMB stores less frequently accessed entries, optimizing the power-performance tradeoff by keeping only essential data in the power-hungry controller memory.

Inventive Principle:

Principle #1Segmentation

3Productivity

If large memory buffer is allocated for ATC, then address translation cache hits are achieved within single 4k IO command, but cost and area increase

Engineering Contradiction:

ImproveATC hit rateVSAvoidmemory buffer area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The ATC is divided into two portions with different sizes and locations. The first portion in controller memory contains the most frequently accessed address translations, ensuring high hit rates for common operations. The second portion in HMB provides additional capacity for less frequently accessed translations, effectively increasing total cache capacity without proportionally increasing controller area.

Inventive Principle:

Principle #1Segmentation

4Productivity

If first portion of ATC is invalidated without deleting second portion, then invalidation efficiency is improved, but data consistency must be maintained

Engineering Contradiction:

Improveinvalidation efficiencyVSAvoiddata consistency

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The invalidation operation is extracted to only affect the first portion of the ATC in controller memory, while the second portion in HMB is left intact. This approach improves invalidation efficiency by avoiding the need to synchronize and clear both portions, while data consistency is maintained through the natural access pattern where translations from the second portion are naturally invalidated when their corresponding first portion entries are removed.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12423244B2Hybrid address translation cache using DRAM

Publication Date: 2025.09.23 SANDISK TECHNOLOGIES LLC

AI summary

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).