Hybrid Analog-Digital Processing Element for Neural Network Accelerators
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Solution Overview
Problem
Existing artificial neural network accelerators face challenges in performing efficient and accurate multiplication-summation operations due to process errors, temperature fluctuations, and overhead in analog signal processing, particularly when dealing with bit-precision weights of 8 bits or more.
Innovation Solution
A processing element comprising an analog operation circuit, analog-to-digital converters (ADCs), and a digital operation circuit, which receives input data, performs multiplication operations based on bit-precision weights, converts output currents into digital codes, and performs addition and summation operations to generate high bit-precision results, enabling efficient analog and digital signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all operations are performed in analog form, then processing speed is improved, but measurement precision deteriorates due to process errors and temperature fluctuations
Solution Approach 1:
The processing element is segmented into distinct analog and digital sections. The analog operation circuit performs multiplication operations at high speed, while separate ADCs and digital operation circuits handle precision accumulation operations. This segmentation allows each section to operate in its optimal domain without compromising overall performance.
Solution Approach 2:
ADCs serve as intermediary components that bridge the analog and digital domains. They convert the analog output currents from the multiplication operation into digital codes that can be accurately accumulated, thus maintaining both the speed benefits of analog processing and the precision requirements of accumulation operations.
2Measurement precision
If high bit-precision operations are performed using analog signals, then measurement precision is improved, but device complexity increases due to overhead of analog signal processing
Solution Approach 1:
The processing element divides functionality into specialized analog and digital sections. The analog operation circuit is dedicated to multiplication, while the digital operation circuit handles accumulation. This segmentation reduces the complexity burden on any single component compared to a fully analog high-precision system.
Solution Approach 2:
The patent replaces complex analog signal processing mechanisms with a hybrid approach using ADCs and digital circuits for accumulation operations. This substitution simplifies the overall system by using well-established digital logic rather than complex analog circuits to achieve high bit-precision accumulation.
3Use of energy by moving object
If analog operation circuit is used for multiplication, then energy consumption is reduced, but reliability deteriorates due to process errors
Solution Approach 1:
The processing element segments the computational tasks so that energy-efficient analog circuits handle multiplication while reliable digital circuits handle accumulation. This segmentation allows the system to benefit from the low power consumption of analog operations without compromising overall reliability, as the critical accumulation function is performed in the reliable digital domain.
Solution Approach 2:
ADCs act as intermediaries that transfer the results from the energy-efficient analog multiplication circuit to the reliable digital accumulation circuit. This intermediary conversion ensures that the benefits of analog energy efficiency are preserved while the final results achieve the reliability of digital processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces operation errors, improves energy efficiency, supports flexible bit-precision operations, and enables low-power design for artificial neural network accelerators by simultaneously processing analog and digital signals, enhancing data flow and resource utilization.
Implementation Method 1
an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents, the one or more output currents associated with a multiplication operation of the input data with weights, the multiplication operation based on a bit-precision of stored weights
Implementation Method 2
one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes
Implementation Method 3
a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the stored weights and to perform a summation operation on a resulting value of the addition operation based on a bit-precision of the input data
Data Source
AI summary
A processing element includes an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents associated with a multiplication operation of the input data and weights based on a bit-precision of stored weights, one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes, and a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the weight and to perform a summation operation on a resultant value of the addition operation based on a bit-precision of the input data.