Hybrid Antifuse OTP Memory Cell Low-Voltage Design
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Solution Overview
Problem
Antifuse One-Time Programmable (OTP) memory cells face challenges in achieving high structural simplicity and integration density due to the need for high-voltage transistors, which occupy more silicon area and increase costs, while antifuse capacitors require thinner gate dielectric layers for easier programming.
Innovation Solution
The development of an antifuse OTP memory cell with a hybrid structure incorporating a low-voltage gate dielectric layer and high-voltage junctions, or a combination of both, for both the select transistor and antifuse capacitor, allowing for smaller silicon footprint and efficient programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors are used to program the antifuse, then the programming function is achieved, but the silicon area increases and integration density decreases
Solution Approach 1:
The patent applies different voltage characteristics to different parts of the transistor: the gate dielectric layer uses thin-film technology for low-voltage operation, while the source/drain junctions are designed as high-voltage junctions. This local differentiation allows the transistor to achieve high-voltage programming capability at the junction level while maintaining low-voltage gate control, thereby reducing the silicon area compared to conventional high-voltage transistors.
Solution Approach 2:
The transistor structure combines thin-film gate dielectric materials with high-voltage junction designs, creating a hybrid device that integrates both low-voltage and high-voltage characteristics. This composite approach enables the select transistor to function as both a low-voltage device (for area efficiency) and a high-voltage device (for programming capability).
2Ease of manufacture
If thin gate dielectric layer is used in antifuse capacitor, then programming becomes easier, but high-voltage junctions are required which increase silicon area
Solution Approach 1:
The antifuse capacitor structure employs thin gate dielectric layer locally at the gate region to facilitate easy programming through standard low-voltage processes, while the source and drain are formed as high-voltage junctions. This localized thin-film approach enables efficient programming without requiring the entire device structure to occupy large silicon area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon area usage, enhances integration density, and improves programming yield while maintaining low-voltage operation, effectively addressing the need for simpler and more densely integrated OTP memory cells.
Implementation Method 1
a thin gate dielectric layer...which enables a low-voltage select transistor device
Implementation Method 2
a high-voltage junction or a mixed high-voltage and low-voltage junctions, for both high voltage programming and smaller silicon area
Data Source
AI summary
An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.