Hybrid Asynchronous Gate Conversion for Low-Area Critical Paths

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Solution Overview

Problem

Existing synchronous integrated circuits (ICs) with analog and RF components face issues of increased noise and vulnerability to side channel attacks due to synchronized switching, while converting to asynchronous circuits using Null Convention Logic (NCL) gates results in significant area overhead.

Innovation Solution

Implement hybrid equivalent gates with synchronous and dual-rail asynchronous inputs and outputs, replacing only critical path gates in synchronous circuits to maintain circuit performance and reduce area overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If Null Convention Logic (NCL) gates are used to generate asynchronous circuits, then noise and side channel attack vulnerability are reduced, but circuit area significantly increases

Engineering Contradiction:
Improvenoise and side channel attack vulnerabilityVSAvoidcircuit area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The circuit is divided into critical path gates and non-critical path gates. Only critical path gates are converted to hybrid equivalent gates, while non-critical path gates remain as standard Boolean gates. This segmentation allows selective application of asynchronous conversion, reducing overall area overhead while maintaining security and noise reduction benefits along the critical path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different gate types are applied to different locations in the circuit based on their importance. Critical path gates use hybrid equivalent gates with dual-rail asynchronous inputs and outputs for enhanced security, while non-critical path gates use standard Boolean gates for area efficiency. This local differentiation optimizes the balance between security and area.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If all Boolean gates are replaced with hybrid equivalent gates, then asynchronous operation is achieved, but circuit area increases significantly

Engineering Contradiction:
Improveasynchronous operation capabilityVSAvoidcircuit area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The circuit is segmented into critical path and non-critical path portions. Only critical path gates are converted to hybrid equivalent gates to achieve essential asynchronous operation, while non-critical path gates remain synchronous. This selective conversion provides asynchronous capability where needed without the full area overhead of complete conversion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of converting all gates to hybrid equivalent gates (excessive action), only the necessary critical path gates are converted (partial action). This partial conversion achieves sufficient asynchronous operation for security and noise reduction while minimizing area overhead.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250298949A1Area efficient asynchronous circuit generator
Publication Date: 2025.09.25 UNIVERSITY OF CINCINNATI
  • US20250298949A1 patent drawing
  • US20250298949A1 patent drawing
  • US20250298949A1 patent drawing

AI summary

An apparatus may comprise a controller programmed to receive information about a synchronized digital circuit comprising a plurality of Boolean gates, determine a critical path through each synchronized, combination subcircuit block of the digital circuit, identify a first set of Boolean gates among the plurality of Boolean gates positioned in the critical path, determine a hybrid equivalent gate for each Boolean gate among the first set of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output, and generate a modified digital circuit by replacing each Boolean gate among the first set of Boolean gates with a corresponding hybrid equivalent gate.