Hybrid Binary Emulation for Cross-Architecture Performance
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Solution Overview
Problem
Software emulation systems face performance delays and scalability issues when translating instructions between guest and native computer architectures due to incompatibilities, such as memory models and data types, leading to costly memory barriers and manual data marshaling requirements.
Innovation Solution
The implementation of hybrid binaries that compile guest source code into native architecture binary code using specialized thunks to handle incompatibilities, allowing native execution and reducing the need for runtime cross-compilation, while maintaining compatibility with the original guest source code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic translation is used to translate x86 instructions to ARM instructions at runtime, then compatibility between guest and native architectures is achieved, but execution performance deteriorates due to translation delays
Solution Approach 1:
The patent pre-translates x86 instructions to ARM instructions before runtime execution, creating a pre-translated binary that can execute directly on ARM hardware without real-time translation overhead. This eliminates the performance penalty of dynamic translation while maintaining architecture compatibility.
Solution Approach 2:
The patent introduces an intermediary toolchain that translates x86 source code to ARM binary code through a multi-step process involving x86 compilation to intermediate representation, then to ARM assembly and binary. This intermediary translation layer resolves the incompatibility between x86 and ARM architectures without requiring runtime translation.
2Reliability
If memory barriers are aggressively generated to emulate x86 strongly ordered semantics on ARM, then memory ordering compatibility is achieved, but execution performance deteriorates due to the cost of memory barriers
Solution Approach 1:
The patent changes the memory ordering parameters by targeting ARM's weaker memory model directly in the pre-translation process. Instead of forcing strong ordering through barriers, the translation generates code that naturally conforms to ARM's memory model, eliminating the need for expensive memory barrier instructions while maintaining correct behavior for the target architecture.
3Adaptability or versatility
If data type marshaling is performed at runtime to handle different data types between guest and native architectures, then data compatibility is achieved, but execution performance deteriorates due to marshaling overhead
Solution Approach 1:
The patent performs data type translation during the pre-compilation phase rather than at runtime. The toolchain translates x86 source code with specific data types to ARM code with appropriate data types before execution, eliminating the need for runtime marshaling operations and associated performance overhead.
4Productivity
If a single processor is used to eliminate memory barrier generation, then execution performance improves, but parallel processing capability deteriorates
Solution Approach 1:
The patent resolves multi-core compatibility issues during pre-translation by generating ARM code that correctly handles memory ordering for parallel execution. The toolchain translates synchronization primitives and memory access patterns to be compatible with ARM's memory model, enabling correct multi-core execution without requiring conservative single-processor defaults.
Data Source
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Figure 3A~3B
AI summary
One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a target binary, wherein the call is in a format for the guest architecture. The method further includes determining that the call is to a binary that is a hybrid binary. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code and a specialized thunk to handle an incompatibility between the guest architecture and the native architecture. The method further includes invoking the specialized thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.