Hybrid BIST Switching Circuitry for Embedded Memory Timing and Area
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Solution Overview
Problem
Existing BIST operations on embedded memory in SoCs face challenges in optimizing timing and area usage due to the positioning of BIST switching circuitry either outside or within the embedded memory, leading to increased routing congestion and space occupation, which affects overall SoC performance.
Innovation Solution
Implementing hybrid BIST switching circuitry with dynamic BIST switching circuitry external to the embedded memory for timing-critical signals and fixed BIST switching circuitry within the embedded memory for non-time-critical signals, utilizing data clubbing techniques to reduce routing complexity and optimize timing and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If BIST switching circuitry is positioned external to the embedded memory, then timing-critical signal performance is improved, but routing congestion and area usage increase
Solution Approach 1:
The BIST switching circuitry is segmented into two parts: dynamic BIST switching circuitry positioned external to the embedded memory for timing-critical signals, and fixed BIST switching circuitry integrated within the embedded memory for non-timing-critical signals. This segmentation allows each part to be optimized for its specific function and location, resolving the contradiction between external positioning benefits and routing congestion drawbacks.
Solution Approach 2:
Different positioning strategies are applied to different parts of the BIST switching circuitry based on local requirements: dynamic switching circuitry is placed externally where timing performance is critical, while fixed switching circuitry is integrated internally where area efficiency is more important. This local quality approach optimizes the overall system by matching circuitry placement to functional requirements.
2Area of stationary object
If BIST switching circuitry is integrated within the embedded memory, then area usage is reduced, but timing-critical signal performance deteriorates
Solution Approach 1:
The BIST switching circuitry is divided into dynamic and fixed components with different positioning strategies. The dynamic portion is external for timing optimization, while the fixed portion is internal for area optimization, resolving the contradiction between integrated positioning benefits and timing performance drawbacks.
Solution Approach 2:
The fixed BIST switching circuitry is integrated within the embedded memory block, utilizing local resources and reducing overall routing area. This internal integration is applied specifically to non-timing-critical signals, allowing area optimization without sacrificing timing performance for critical paths.
3Speed
If hybrid BIST switching circuitry is implemented, then timing and area usage are optimized, but device complexity increases
Solution Approach 1:
The hybrid BIST switching circuitry segments functionality into dynamic and fixed components with distinct positioning and control mechanisms. This segmentation enables independent optimization of each component, managing complexity by allowing separate design and verification of dynamic and fixed portions rather than requiring complex integration of a single unified system.
Data Source
AI summary
Various embodiments are directed to example system-on-chip integrated circuits configured to perform built-in self test operations on an embedded memory. An example system-on-chip integrated circuit includes dynamic BIST switching circuitry and an embedded memory. The dynamic BIST switching circuitry is configured to generate a dynamic BIST output based on a test state. The embedded memory is configured to receive the dynamic BIST output. The embedded memory includes fixed BIST switching circuitry configured to generate a fixed BIST output based on the test state. Wherein the fixed BIST switching circuitry is internal to the embedded memory, and the dynamic BIST switching circuitry is external to the embedded memory.