Hybrid Block Sub-Block Erase for Flash Memory Endurance
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Solution Overview
Problem
In storage systems with large block sizes, erasing and rewriting data is time-consuming and decreases performance, as the entire block must be erased and relocated, leading to issues with program disturb and high bit error rates due to adjacent programmed sub-blocks.
Innovation Solution
Implementing a sub-block erase operation where one sub-block is erased while the other is programmed, using a controller to manage sub-blocks of different bit capacities, such as SLC and MLC modes, to minimize bit error rates and allow for partial-block erase modes, reducing block relocation and improving endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire block is erased to remove data from part of a block, then data erasure is achieved, but the operation is time-consuming and decreases performance
Solution Approach 1:
The patent divides a memory block into multiple sub-blocks that can be independently erased. Instead of erasing the entire block when only part of the data needs to be removed, the system erases only the specific sub-block containing the target data. This segmentation enables partial block erasure operations, significantly reducing erase time and improving performance while maintaining complete data erasure reliability within the targeted sub-block.
2Ease of operation
If the entire block is erased and relocated, then data management is simplified, but the frequency of block relocations increases reducing endurance
Solution Approach 1:
By segmenting the block into independently erasable sub-blocks, the patent enables selective erasure of only the necessary portions. This reduces the frequency of full block erasures and relocations, thereby decreasing wear on the memory chip and improving endurance while maintaining effective data management through the controller's ability to track and manage sub-block states.
Solution Approach 2:
The patent applies different operational characteristics to different sub-blocks within the same block. Some sub-blocks can be erased and reused while others remain intact and programmed, allowing the system to optimize for both data management efficiency and chip endurance by treating different regions of the block according to their specific needs.
3Quantity of substance
If adjacent sub-blocks are programmed with high bit capacity, then storage density is improved, but bit error rates increase due to program disturb
Solution Approach 1:
The patent implements different programming modes for different sub-blocks within the same physical block. Sub-blocks that are frequently accessed or require high reliability can be programmed in SLC mode with lower bit capacity but better error characteristics, while other sub-blocks can use MLC or TLC modes for higher storage density. This local differentiation allows the system to optimize for both storage capacity and bit error rate based on specific sub-block requirements.
Solution Approach 2:
The patent dynamically changes the programming parameters (bits per cell) for different sub-blocks based on their access patterns and reliability requirements. By adjusting the programming mode between SLC, MLC, and TLC for different sub-blocks, the system can adaptively balance storage density against bit error rate, achieving optimal performance for each sub-block's specific use case.
Data Source
AI summary
A storage system and method for using hybrid blocks with sub-block erase operations are provided. In one embodiment, a storage system is provided comprising a memory comprising a block, wherein the block comprises a first sub-block and a second sub-block; and a controller in communication with the memory. The controller is configured to erase the first sub-block, wherein the second sub-block is programmed; and program the first sub-block to fewer bits per cell than the second sub-block is programmed to. Other embodiments are provided.