Hybrid Bond Junction Circuit for Vertical SoIC Die Connections
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges with increased resistance between stacked semiconductor dies due to the need for through-substrate vias, which hinder efficient electrical connections and reduce integration density.
Innovation Solution
A vertical system of integrated chips (SoIC) with a hybrid bond contact junction circuit allows for direct perpendicular connections between semiconductor dies, reducing resistance and increasing the number of connected dies by using a bonding redistribution layer and copper wire connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used to connect stacked semiconductor dies, then electrical connections can be established between dies, but resistance increases and integration density decreases
Solution Approach 1:
The patent transitions from planar interconnects to three-dimensional vertical interconnects using stacked semiconductor dies. Multiple dies are bonded together in a vertical stack, with interconnects extending through the thickness of the stack, enabling direct electrical pathways between non-adjacent dies without requiring through-substrate vias in a single thick substrate.
Solution Approach 2:
The patent divides a single thick semiconductor substrate into multiple thinner stacked dies. Each die can be independently processed and optimized, and the segmentation allows for shorter current paths within each die while maintaining overall connection functionality through the stack.
2Productivity
If the number of stacked semiconductor dies is increased, then integration density improves, but resistance between dies increases
Solution Approach 1:
The patent introduces intermediate connection structures at each die interface, including bonding pads, metallization layers, and transition regions that facilitate low-resistance electrical contact between stacked dies. These intermediaries enable efficient current transfer across die boundaries, reducing overall stack resistance.
Solution Approach 2:
The patent employs composite interconnect structures combining multiple materials with complementary properties, such as copper or aluminum metallization layers bonded to corresponding layers in adjacent dies, creating parallel current pathways that reduce resistance while supporting higher integration densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a more direct and efficient connection between non-adjacent semiconductor dies, reducing overall resistance and increasing integration density in vertical SoIC devices.
Implementation Method 1
a bonding layer for bonding the second semiconductor die to the first semiconductor die. The junction circuit may be formed in the bonding layer
Data Source
AI summary
A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.