Hybrid-Bonded Capacitor Die Stack for Low-ESL IC Power Delivery
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Solution Overview
Problem
Integrating capacitors and integrated circuits in electronic systems while avoiding wire bonding or solder mounting, which is challenging due to the need for high capacitance, low ESL, and ESR, and efficient power management in complex electronic systems.
Innovation Solution
A circuit assembly comprising an IC die and a stack of capacitor dies with hybrid bonding layers for electrical connection, allowing capacitors to be integrated without wire bonding or solder mounting, using deep trench capacitors or MIM stack capacitors, and enabling efficient power and signal transmission through conductive vias and interface bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding or solder mounting is used to integrate capacitors and ICs, then electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the capacitor structure with the IC substrate by forming capacitors directly on the substrate using the same semiconductor fabrication processes. This integration eliminates the need for separate capacitor components, wire bonding, or solder mounting, thereby reducing device complexity and easing manufacturing while maintaining electrical connection functionality.
Solution Approach 2:
The IC substrate serves multiple functions: it acts as both the circuit board for mounting ICs and as the substrate for forming integrated capacitors. This multi-functionality eliminates the need for separate capacitor components and complex interconnection processes, directly addressing the contradiction between ease of manufacture and device complexity.
2Reliability
If conventional capacitors are used, then capacitance function is provided, but equivalent series inductance (ESL) and equivalent series resistance (ESR) are high
Solution Approach 1:
The patent implements local quality by creating capacitors with specific structural characteristics directly at the location where they are needed on the IC substrate. The capacitors are formed with optimized local geometry (e.g., interdigitated electrode patterns, controlled thickness profiles) to minimize ESL and ESR locally, thereby improving overall capacitor performance without requiring external components.
Solution Approach 2:
The patent transitions from conventional planar capacitor designs to three-dimensional capacitor structures formed within the substrate depth. By utilizing vertical stacking and depth-dependent electrode configurations, the patent reduces the effective current path length and parasitic inductance, thereby lowering ESL and ESR while maintaining the capacitance function.
3Reliability
If capacitors are integrated directly on IC substrate, then high capacitance and low ESL/ESR are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves the desired capacitor performance by optimizing fabrication parameters such as deposition thickness, etch depth, and electrode pattern dimensions. By carefully controlling these parameters within standard semiconductor manufacturing tolerances, the patent achieves high capacitance and low ESL/ESR without requiring extraordinary manufacturing precision, thus resolving the contradiction between performance and manufacturability.
Data Source
AI summary
A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.