Hybrid-Bonded Semiconductor Package for Thinner 3D Chip Stacking
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Solution Overview
Problem
The existing semiconductor package structures with solder ball connections for stacked DRAM chips face issues of increased thickness and reduced reliability due to spacing requirements, affecting integration and signal transmission.
Innovation Solution
A semiconductor package structure utilizing a hybrid bonding layer with conductive structures that directly bond adjacent chips, reducing spacing and thickness, and enhancing signal transmission reliability through direct bonding and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder ball connections are used for stacked DRAM chips, then electrical connection between chips is achieved, but package thickness increases and reliability decreases
Solution Approach 1:
The patent removes the solder ball connection layer and associated spacing requirements from the chip stacking structure. By eliminating this intermediate connection method and replacing it with direct face-to-face bonding, the source of increased thickness is extracted from the system, allowing chips to be positioned closer together while maintaining connection reliability.
Solution Approach 2:
The patent introduces a bonding interface directly between adjacent chip surfaces, eliminating the need for solder balls as intermediaries. This direct bonding approach uses bonding pads and metallurgical bonding to establish electrical and mechanical connections without requiring the additional thickness that solder ball connections demand.
2Productivity
If solder ball connections are used for stacked DRAM chips, then electrical connection is established, but spacing requirements increase reducing integration density
Solution Approach 1:
The patent extracts the spacing requirement constraint by eliminating solder ball connections. Without the need for solder balls and their associated clearance zones, chips can be placed in direct contact or near-contact configuration, maximizing the number of chips that can be integrated within a given vertical space.
Solution Approach 2:
The patent transitions from a spaced-out three-dimensional arrangement with solder balls to a compact face-to-face stacking configuration. This dimensional reorganization allows chips to occupy adjacent positions in the vertical dimension without requiring lateral spacing, thereby increasing integration density.
3Length of stationary object
If direct bonding is used to reduce spacing, then package thickness decreases, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary alignment and preparation of bonding surfaces before the actual bonding process. By pre-positioning chips with precise alignment features and preparing bonding pads in advance, the manufacturing process becomes more controllable and less complex, enabling direct bonding to achieve reduced thickness without excessive manufacturing difficulty.
Data Source
AI summary
The present disclosure provides a semiconductor package structure and a fabrication method thereof. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, wherein the first semiconductor chip includes at least one conductive structure; the conductive structure includes a first connection structure and a second connection structure both extending along the first direction, and an interconnection structure located between the first connection structure and the second connection structure in the first direction; and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first hybrid bonding layer located between two adjacent ones of the first semiconductor chips in the first direction, wherein the first hybrid bonding layer includes at least one first bonding structure coupled with the conductive structures in the two adjacent ones of the first semiconductor chips.