Hybrid-Bonded Semiconductor Chip Structure for Flat Bonding Surfaces
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Solution Overview
Problem
Conventional semiconductor chip structures face challenges in achieving good bonding reliability between semiconductor chips due to step differences in the uppermost final wiring patterns between chip and scribe lane regions.
Innovation Solution
A semiconductor chip structure is developed with improved bonding reliability by hybrid bonding the first bonding insulating layer and bonding electrode of the first semiconductor chip with the second bonding insulating layer and bonding electrode of the second semiconductor chip, ensuring flat bonding surfaces without step differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor chips with step differences in uppermost final wiring patterns are used for bonding, then chip manufacturing is simpler, but bonding reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by forming bonding electrodes and bonding insulating layers on both semiconductor chips before the bonding process. This advance preparation ensures that when the chips are bonded, the bonding surfaces are already properly structured, eliminating step differences and ensuring reliable bonding without requiring complex post-bonding adjustments.
Solution Approach 2:
The patent applies local quality by making the bonding surfaces (bonding electrodes and bonding insulating layers) have different properties from the rest of the chip structure. Specifically, these bonding surfaces are designed to be flat and have controlled thicknesses to eliminate step differences, while other parts of the chip can maintain their conventional structures with step differences.
2Manufacturing precision
If bonding surfaces with step differences are used, then manufacturing process is simpler, but bonding flatness deteriorates
Solution Approach 1:
The bonding insulating layers are formed in advance on the bonding surfaces with controlled thicknesses to compensate for underlying step differences. This preliminary formation of insulating layers creates flat bonding surfaces before the actual bonding process, achieving high bonding precision without requiring complex real-time adjustments during bonding.
3Reliability
If conventional wiring patterns with step differences are used, then chip design is simpler, but bonding performance deteriorates
Solution Approach 1:
The patent applies local quality by creating specialized bonding layers (bonding electrodes and bonding insulating layers) with specific properties only at the bonding surfaces, while the rest of the chip wiring patterns can remain conventional. The bonding insulating layers have controlled thicknesses to eliminate step differences locally at bonding areas without affecting the overall chip design simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid bonding approach enhances the bonding reliability between semiconductor chips, ensuring proper functionality and performance by eliminating step differences and improving the flatness of bonding surfaces.
Implementation Method 1
the first bonding insulating layer and the first bonding electrode in the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode in the second bonding wiring layer
Data Source
AI summary
A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.