Hybrid-Bonded Die Stack Structure for Dense SoIC Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Circuit (SoIC) components due to limitations in current packaging processes, which hinder the achievement of smaller, faster, and more energy-efficient devices.
Innovation Solution
A method for fabricating a die stack structure involving top and bottom tier semiconductor dies bonded through hybrid bonding, with a redistribution circuit structure and insulating encapsulation, allowing for efficient integration and protection of semiconductor components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging processes are used for SoIC components, then the packaging can be achieved with existing technology, but the integration density and device performance cannot be sufficiently improved
Solution Approach 1:
The packaging process is divided into distinct stages: forming separate first and second recesses in the substrate, selectively bonding semiconductor dies to specific recesses, and performing singulation after bonding. This segmentation allows complex packaging operations to be broken down into manageable steps that achieve high integration density without overwhelming process complexity.
Solution Approach 2:
The patent transitions from conventional two-dimensional packaging to three-dimensional die stacking. Multiple semiconductor dies are bonded vertically on top of each other on the substrate, creating a stacked configuration that significantly increases integration density by utilizing the vertical dimension rather than only horizontal placement.
2Manufacturing precision
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated into a given area, but manufacturing and packaging become increasingly difficult
Solution Approach 1:
Recesses are pre-formed in the substrate before semiconductor dies are bonded to them. This preliminary action creates prepared bonding locations with appropriate depth and geometry, making the subsequent die bonding process easier and more precise. The recesses act as guides and support structures that facilitate accurate placement and bonding of small-feature-size dies.
Solution Approach 2:
The substrate with pre-formed recesses serves as an intermediary structure between the semiconductor dies and the final packaged product. The recesses provide mechanical support, alignment references, and bonding surfaces that simplify the handling and integration of miniaturized dies, making the overall manufacturing process more manageable despite reduced feature sizes.
3Volume of moving object
If multiple semiconductor dies are stacked to achieve compact packaging, then device compactness is improved, but bonding precision and reliability become more critical and difficult to achieve
Solution Approach 1:
Different regions of the substrate are created with different properties: some recesses are designed for bonding specific types or sizes of semiconductor dies. The recesses have localized geometric features tailored to match the specific dies intended for each location, ensuring precise bonding. This local customization of recess geometry to match specific die characteristics improves bonding precision in multi-die stacks.
Solution Approach 2:
The recesses are designed with dimensions and geometries that provide built-in alignment and mechanical support before bonding occurs. The recess walls and bottom surfaces are configured to cushion and support the dies during bonding, preventing misalignment and ensuring consistent bonding quality across multiple dies in the stack, thereby addressing precision requirements beforehand.
Data Source
AI summary
A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.