Hybrid-Bonded HBM Stack for Higher Density Without Taller Packages
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Solution Overview
Problem
As integrated circuits move to smaller technology nodes, there is a challenge in increasing performance without increasing package size, particularly in high bandwidth memory (HBM) stacks where the tradeoff between the number of vertically stacked memory dies and package height is significant.
Innovation Solution
The solution involves forming memory dies with at least two layers of memory devices using hybrid bonding of BEOL interconnect structures from two memory wafers, allowing for increased memory density without increasing the overall package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked memory dies is increased to improve memory density, then memory density is improved, but package height increases
Solution Approach 1:
The patent transitions from vertical stacking (single dimension) to lateral stacking within a single die (adding another dimension). Multiple memory device layers are arranged side-by-side in the lateral direction within a single memory die, allowing increased memory density without increasing package height in the vertical direction.
Solution Approach 2:
The patent divides a single memory die into multiple distinct memory device layers, each containing memory cells. This segmentation allows multiple layers to be integrated within a single die footprint, effectively doubling or tripling memory density without requiring additional vertical stacking that would increase package height.
2Quantity of substance
If multiple layers of memory devices are integrated into a single memory die, then memory density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms multiple memory device layers simultaneously within a single die during the manufacturing process, rather than stacking completed dies vertically. This preliminary integration of multiple layers before final packaging simplifies the overall manufacturing complexity compared to post-fabrication stacking methods.
Solution Approach 2:
The patent merges multiple memory device layers into a single integrated memory die structure, combining what would traditionally be separate stacked dies into one unified component. This merging reduces the number of discrete stacking operations and interconnect interfaces required, thereby reducing manufacturing complexity.
3Length of stationary object
If conventional vertical stacking is used, then package height is reduced, but memory density is limited
Solution Approach 1:
The patent employs lateral stacking of memory device layers within a single die plane, utilizing the horizontal dimension rather than relying solely on vertical stacking. This dimensional shift enables doubled or tripled memory density while maintaining a compact package height suitable for conventional HBM applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles the memory density of the memory stack while maintaining comparable package height to conventional HBM stacks, thereby enhancing performance without sacrificing yield rates or increasing package size.
Implementation Method 1
directly bonding the second BEOL interconnect structure of the second memory wafer structure to the first BEOL interconnect structure of the first memory wafer structure through hybrid bonding
Data Source
AI summary
A memory device and formation thereof. The memory device includes a stack of memory dies. Each memory die in the stack of memory dies includes two or more layers of memory devices.